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Logic Analyzer 的代码
counter2.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter2 is
Port ( set,rd : in std_logic;
clk : in std_logic;
sztop.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sztop is
Port ( clk1,sz: in std_logic;
ringg:out std_logic;
h1
counter10.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( set : in std_logic;
clk : in std_logic;
reg_8rst.vhd
-- "reg_8rst.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gene
reg_pc.vhd
-- "reg_pc.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
reg_s.vhd
-- "reg_s.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General
reg_8t.vhd
-- "reg_8t.vhd"
--
-- Copyright (C) 1998 Ernesto Romani (romani@ascu.unian.it)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Genera
count_6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count_6 IS
PORT(clk,clr: IN STD_LOGIC;
co:OUT STD_LOGIC;
qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
count_10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count_10 IS
PORT(clk,clr: IN STD_LOGIC;
co:OUT STD_LOGIC;
qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0
multi8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY multi8 IS
PORT(
clk,start:IN STD_LOGIC;--乘法启动信号，高电平复位与加载，低电平运算
a,b :IN STD_LOGIC_V