multi8.vhd

出租车计费器,VHDL实现

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
ENTITY  multi8  IS
    PORT(
         clk,start:IN STD_LOGIC;--乘法启动信号，高电平复位与加载，低电平运算                                
              a,b :IN STD_LOGIC_VECTOR(7 DOWNTO 0);  --8位被乘数，乘数          
           multend:OUT STD_LOGIC;  --乘法运算结束标志            
              dout:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));  --16位乘积输出          
END  multi8;

ARCHITECTURE  struc  OF multi8  IS
   COMPONENT  sign8
       PORT(
            clk,start:IN STD_LOGIC;
        clkout,rstall,multend:OUT STD_LOGIC);
   END  COMPONENT;
   COMPONENT  andari
       PORT(
         abin:IN STD_LOGIC;
          din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         dout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
   END  COMPONENT;
   COMPONENT  add8
       PORT(
           cin:IN STD_LOGIC;
          a,b :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            s :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          cout:OUT STD_LOGIC); 
   END  COMPONENT;
   COMPONENT  sreg8
       PORT(
         clk,load:IN STD_LOGIC;
              din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               qb:OUT STD_LOGIC);
   END  COMPONENT;
   COMPONENT  reg16
       PORT(
              clk:IN STD_LOGIC;
               clr:IN STD_LOGIC;
               d:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
               q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
   END  COMPONENT;
   SIGNAL gndint,intclk,rstall,qb:STD_LOGIC;
   SIGNAL andsd:STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL dtbin:STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL dtbout:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
   dout<=dtbout;
   gndint<='0';
   U1:sign8 PORT MAP(clk,start,intclk,rstall,multend);
   U2:sreg8 PORT MAP(intclk,rstall,b,qb);
   U3:andari PORT MAP(qb,a,andsd);
   U4:add8 PORT MAP(gndint,dtbout(15 DOWNTO 8),andsd,dtbin(7 DOWNTO 0),dtbin(8));
   U5:reg16 PORT MAP(intclk,rstall,dtbin,dtbout);
END struc;