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找到约 10,000 项符合
Logic Analyzer 的代码
top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
port( clk0 : in std_logic;--50MHz基准时钟信号;
addbcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity addbcd is
port( -- data : in std_logic_vector(7 downto 0);
bcd1 : in std_logic_v
cnt31.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt31 is
port(clk,en :in std_logic;
co:out std_logic;
q :buffer std_logic_vector(1 downto
bjq1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bjq1 is
port(d,m :in std_logic_vector(3 downto 0);
sel :in std_logic_ve
latch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE Behavior OF latch IS
BEGIN
PRO
shift.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY lpm ;
USE lpm.lpm_components.all ;
ENTITY shift IS
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
Shiftin, Load :
subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
proc.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE work.subccts.all ;
ENTITY proc IS
PORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Reset, w : IN STD_
subccts.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE subccts IS
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_L
shiftn.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY shiftn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Clock : IN STD_LOGIC ;
L, w : IN S