cnt31.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt31 is
	port(clk,en	:in std_logic;
           co:out std_logic;
        q  	:buffer std_logic_vector(1 downto 0));
end cnt31;

architecture behav of cnt31 is
begin
process(en,clk)
begin
if(en='0')then
q<="00";co<='0';
elsif (clk'event and clk='1') then
if q="10" then q<="00";co<='1';

ELSE   
q<=q+1;co<='0';
end if;
end if;
end process;
end behav;