top.vhd

数字式移相信号发生器可以产生预置频率的正弦信号

library IEEE;
      use IEEE.STD_LOGIC_1164.ALL;
      use IEEE.STD_LOGIC_ARITH.ALL;
      use IEEE.STD_LOGIC_UNSIGNED.ALL;
      entity top is
          port( clk0 : in std_logic;--50MHz基准时钟信号;
           set0, butt1, butt2 : in std_logic;--确定按键,幅值增,减;
            butt0,sw1_0,sw2_0 : in std_logic; --选折开关,量程扩长* 10档;
           data3, data2, data1,data0 : in std_logic_vector(3 downto 
      0);--拨码盘BCD码输入;
            lcd : out std_logic_vector(7 downto 0);--BCD码输出;
           shift : out std_logic_vector(3 downto 0);--位选信号;
            dd0, dd1 : out std_logic_vector(7 downto 0);--控制D/A进行幅度调节;
           a0, a1 : out std_logic_vector(9 downto 0));--正弦波幅值输出;
      end top;
      architecture Behavioral of top is
       component move_phase
          Port ( clk4:in std_logic;
                     sw1,sw2:in std_logic;
                             --sign1:in std_logic;
                              --d_4 : out std_logic_vector(7 downto 0)
                             bcd00_4,bcd10_4,bcd20_4,bcd30_4:in integer range 0 
      to 10;
                             shift_4:out std_logic_vector(3 downto 0);
                             lcd_4:out std_logic_vector(7 downto 0));
       end component;
        component wave_generator
          Port (clk1 : in std_logic;
                      f_1:in std_logic_vector(8 downto 0);
                 d : out std_logic_vector(7 downto 0));
       end component;
      component fupin_control
         Port ( clk2,sw1_2,sw2_2 ,set_2,butt0_2,butt1_2,butt2_2: in std_logic;
                 --tmp_2 : in integer range 0 to 9999;
                            data0_2,data1_2,data2_2,data3_2:in 
      std_logic_vector(3 downto 0);
                 d_2 : in std_logic_vector(7 downto 0);
                               dd0_2, dd1_2 : out std_logic_vector(7 downto 0);
                 a0_2, a1_2 : out std_logic_vector(9 downto 0);
                             f_2:out std_logic_vector(8 downto 0));
       end component;
       component yima
          Port (clk3,set3:in std_logic;
                     --amp0,amp1:in std_logic;
                            sw1_3,sw2_3:in std_logic;
                            --tmp :  in integer range 0 to 9999;
                            --tmpp :in std_logic_vector(8 downto 0);
                            data0_3,data1_3,data2_3,data3_3:in 
      std_logic_vector(3 downto 0);
                            bcd00_3,bcd10_3,bcd20_3,bcd30_3 : out integer range 
      0 to 10 );
       end component;
      signal  bcd0_4,bcd1_4,bcd2_4,bcd3_4: integer range 0 to 10;
      signal f_cont:std_logic_vector(8 downto 0);
      signal d_cont :std_logic_vector(7 downto 0);
      begin
         u1:move_phase port 
      map(clk4=>clk0,sw1=>sw1_0,sw2=>sw2_0,bcd00_4=>bcd0_4,bcd10_4=>bcd1_4,bcd20_4=>bcd2_4,bcd30_4=>bcd3_4,shift_4=>shift,lcd_4=>lcd);
             u2:wave_generator port map(clk1=>clk0,f_1=>f_cont,d=>d_cont);
         u3:fupin_control port map 
      (clk2=>clk0,sw1_2=>sw1_0,sw2_2=>sw2_0,set_2=>set0,
                                        
      butt0_2=>butt0,butt1_2=>butt1,butt2_2=>butt2,data0_2=>data0,
                                        
      data1_2=>data1,data2_2=>data2,data3_2=>data3,d_2=>d_cont,dd0_2=>dd0,
                                                                            
      dd1_2=>dd1,a0_2=>a0,a1_2=>a1,f_2=>f_cont);
             u4:yima          port 
      map(clk3=>clk0,set3=>set0,sw1_3=>sw1_0,sw2_3=>sw2_0,data0_3=>data0,data1_3=>data1,data2_3=>data2, 
                                 
      data3_3=>data3,bcd00_3=>bcd0_4,bcd10_3=>bcd1_4,bcd20_3=>bcd2_4,bcd30_3=>bcd3_4);
      end Behavioral;