bjq1.vhd

VHDL的课程设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bjq1 is
port(d,m   :in std_logic_vector(3 downto 0);
sel         :in std_logic_vector(1 downto 0);
        result :out  std_logic);
end bjq1;
architecture behav of   bjq1 is
begin
process(sel)
begin
if(sel="01"and d=m)then
result<='1';
elsif(sel="10"and d=m)then
result<='1';
elsif(sel="11"and d=m)then
result<='1'; 
else 
result<='0';
end if;
end process;
end behav;