addbcd.vhd

来自「2008年北京市大学生电子设计竞赛程序源代码[测频率」· VHDL 代码 · 共 34 行

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     ieee.std_logic_unsigned.all;

entity addbcd is
   port( -- data   : in    std_logic_vector(7 downto 0);
          bcd1   : in   std_logic_vector(15 downto 0);
          bcd2   : in   std_logic_vector(15 downto 0);
          bcd    : out   std_logic_vector(15 downto 0)
          );                           
   end addbcd;


architecture a1 of addbcd is

--signal    bcd_a : std_logic_vector(15 downto 0);
--signal    bcd_b : std_logic_vector(15 downto 0);
signal     a:  std_logic;
constant   b: std_logic:='0';
 component adder 
 Port(   x,y: in  std_logic_vector(15 downto 0);
        cin : in  std_logic;
        sum : out std_logic_vector(15 downto 0);
        cout: out std_logic );
 end component; 

BEGIN

 A1: adder port map (bcd1,bcd2,b,bcd,a);

END;