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Logic Analyzer 的代码
seg7_lut_8_0.vhd
-- SEG7_LUT_8_0.vhd
-- This file was auto-generated as part of a SOPC Builder generate operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all
audiotop.vhd
-------------------------------------------------------------------------------
-- audiotop
--
-- Author(s): James Brennan and Jorgen Peddersen
-- Created: Dec 2000
-- Last Modified: De
remap.vhd
-------------------------------------------------------------------------------
-- remap.vhd
--
-- Created: Dec 2000
-- Last Modified: Dec 2000
--
-- This file only renames signals to nam
uart_clock.vhd
--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KC
lcd1602.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************
top_struct.vhd
-------------------------------------------------------------------------------
-- --
-- 8086VGA - VHDL 8086/8088 VGA IP co
pio_rtl.vhd
-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--