📄 top_struct.vhd
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-------------------------------------------------------------------------------
-- --
-- 8086VGA - VHDL 8086/8088 VGA IP core --
-- Copyright (C) 2007 WInston Zhu --
-- --
-- Contact : mailto: Winston.Zhu@yahoo.com --
-- Web: http://www.openhard.org/myspace/blog/?bid=6926 --
-- --
-------------------------------------------------------------------------------
-- --
-- This library IS free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library IS distributed IN the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found IN the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
--
-- VHDL Architecture web_example.Top.symbol
--
-- Created: by - Hans 27/08/2005
-- Modified: by - Winston 01/08/2007
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Top IS
PORT(
clk : IN STD_LOGIC;
cpu_resetn : IN STD_LOGIC;
rxd1 : IN STD_LOGIC;
rxd2 : IN STD_LOGIC;
dbus_key : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
user_pbx : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
fse_a : OUT STD_LOGIC_VECTOR (22 DOWNTO 0);
ledg : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
outport : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
sram_be_n : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
sram_cs_n : OUT STD_LOGIC;
sram_oe_n : OUT STD_LOGIC;
sram_we_n : OUT STD_LOGIC;
txd1 : OUT STD_LOGIC;
txd2 : OUT STD_LOGIC;
fse_d :INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
green : OUT STD_LOGIC;
red : OUT STD_LOGIC; blue : OUT STD_LOGIC; Hsync : OUT STD_LOGIC; Vsync : OUT STD_LOGIC
);
-- Declarations
END Top ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY CPU;
ARCHITECTURE struct OF Top IS
-- Architecture declarations
-- Internal SIGNAL declarations
SIGNAL csrom : STD_LOGIC;
SIGNAL csramn : STD_LOGIC; SIGNAL cstextram : STD_LOGIC; SIGNAL csdispram : STD_LOGIC; SIGNAL cskey : STD_LOGIC;
SIGNAL abus : STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL biu_error : STD_LOGIC;
SIGNAL dbus_rom : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_disp_ram : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_text_ram : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_ext : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_in_cpu : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_io : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_out_cpu : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL inport : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL intr : STD_LOGIC;
SIGNAL iom : STD_LOGIC;
SIGNAL lock : STD_LOGIC;
SIGNAL nmi : STD_LOGIC;
SIGNAL por : STD_LOGIC;
SIGNAL proc_error : STD_LOGIC;
SIGNAL rdn : STD_LOGIC;
SIGNAL resetn : STD_LOGIC;
SIGNAL sel_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL step_mux : STD_LOGIC;
SIGNAL step_on : STD_LOGIC;
SIGNAL test : STD_LOGIC;
SIGNAL tx2 : STD_LOGIC;
SIGNAL txmon : STD_LOGIC;
SIGNAL wran : STD_LOGIC;
SIGNAL wrn : STD_LOGIC;
SIGNAL we_disp : STD_LOGIC;
SIGNAL we_text : STD_LOGIC;
SIGNAL disp_addr : STD_LOGIC_VECTOR(14 downto 0);
SIGNAL disp_dout : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL clkout : STD_LOGIC;
-- COMPONENT Declarations
COMPONENT cpu86
PORT (
clk : IN STD_LOGIC ;
dbus_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
intr : IN STD_LOGIC ;
nmi : IN STD_LOGIC ;
por : IN STD_LOGIC ;
step_sw : IN STD_LOGIC ;
test : IN STD_LOGIC ;
abus : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
biu_error : OUT STD_LOGIC ;
dbus_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
inta : OUT STD_LOGIC ;
iom : OUT STD_LOGIC ;
lock : OUT STD_LOGIC ;
proc_error : OUT STD_LOGIC ;
rdn : OUT STD_LOGIC ;
resoutn : OUT STD_LOGIC ;
step_mux : OUT STD_LOGIC ;
step_on : OUT STD_LOGIC ;
txmon : OUT STD_LOGIC ;
wran : OUT STD_LOGIC ;
wrn : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT superio_top
GENERIC (
COM_DIVIDER : integer := 15;
TMR_DIVIDER91 : integer := 359256;
UART2_G : boolean := TRUE
);
PORT (
abus : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clk : IN STD_LOGIC ;
dbusin : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inport : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
iom : IN STD_LOGIC ;
rdn : IN STD_LOGIC ;
resetn : IN STD_LOGIC ;
rx1 : IN STD_LOGIC ;
rx2 : IN STD_LOGIC ;
wrn : IN STD_LOGIC ;
dbusout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
outport : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pulse182 : OUT STD_LOGIC ;
tx1 : OUT STD_LOGIC ;
tx2 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT embedded_rom
PORT ( a: IN std_logic_VECTOR(7 downto 0); clk: IN std_logic; spo: OUT std_logic_VECTOR(7 downto 0)); END COMPONENT;
COMPONENT textram PORT(
clk : IN STD_LOGIC; addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
din : IN STD_LOGIC_VECTOR (7 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
we : IN STD_LOGIC ); END COMPONENT; COMPONENT disp_ram PORT( addra: IN STD_LOGIC_VECTOR(14 downto 0); addrb: IN STD_LOGIC_VECTOR(14 downto 0); clka: IN STD_LOGIC; clkb: IN STD_LOGIC; dina: IN STD_LOGIC_VECTOR(7 downto 0);
douta: OUT STD_LOGIC_VECTOR(7 downto 0); doutb: OUT STD_LOGIC_VECTOR(7 downto 0); wea: IN STD_LOGIC ); END COMPONENT;
COMPONENT disp IS PORT( reset : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR (7 downto 0);
addr_out : OUT STD_LOGIC_VECTOR (14 downto 0); red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC; Hsync : OUT STD_LOGIC; Vsync : OUT STD_LOGIC ); END COMPONENT; COMPONENT myclock PORT( CLKIN_IN : IN std_logic; RST_IN : IN std_logic; CLKDV_OUT: OUT std_logic; CLK0_OUT : OUT std_logic; LOCKED_OUT : OUT std_logic ); END COMPONENT;
-- Optional embedded configurations
FOR ALL : cpu86 USE ENTITY CPU.cpu86;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
-- eb1 1
txd2 <= txmon when step_mux='1' else tx2;
-- HDL Embedded Text Block 3 BSP1
-- Board Support Package/Interface
-- BSP 2
-- Reset, need to fix!, mixture of active high and low
por <= cpu_resetn;
-- Address(23)/Databus(32)
fse_a <= "000" & abus;
PROCESS(abus,csramn)
BEGIN
if (csramn='0') then
CASE abus(1 downto 0) IS
when "00" => sram_be_n <= "1110";
when "01" => sram_be_n <= "1101";
when "10" => sram_be_n <= "1011";
when others => sram_be_n <= "0111";
END CASE;
else
sram_be_n <= "1111";
END if;
END PROCESS;
sram_oe_n <= rdn;
sram_we_n <= wran; -- use async wr, this IS negated asserted on the falling edge of clk!
sram_cs_n <= csramn;
-- unused signals
-- Leds and switches
-- Leds active high
ledg(0) <= proc_error;
ledg(1) <= biu_error;
ledg(2) <= step_on;
ledg(3) <= step_mux;
ledg(4) <= '1';
ledg(5) <= not lock;
ledg(6) <= not user_pbx(2);
ledg(7) <= not user_pbx(3); -- use to start the load86 monitor
nmi <= not user_pbx(2); -- test only
-- intr <= not user_pbx(3); -- test only
inport <= "0000" & user_pbx;
-- HDL Embedded Text Block 4 dmux2
-- dmux 1
PROCESS(sel_s, dbus_rom, dbus_text_ram, dbus_disp_ram, dbus_key, dbus_io, dbus_ext)
BEGIN
CASE sel_s IS
when "01110" => dbus_in_cpu <= dbus_rom;
when "10110" => dbus_in_cpu <= dbus_text_ram;
when "11010" => dbus_in_cpu <= dbus_disp_ram;
when "11100" => dbus_in_cpu <= "0000" & dbus_key;
when "11111" => dbus_in_cpu <= dbus_io;
when others => dbus_in_cpu <= dbus_ext;
END CASE;
END PROCESS;
-- HDL Embedded Text Block 7 chip_select2
-- chip_select 4
-- cpu databus IN multiplexer SIGNAL
sel_s <= csrom & cstextram & csdispram & cskey & iom;
--Keyin Register
cskey <= '0' when ((abus(19 downto 0)=X"04000") AND iom='0') else '1';
-- Bootstrap ROM 256 bytes (32 words distribute rom)
-- FFFFF-FF=FFF00
csrom <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- Program RAM 8Kbyte
cstextram <= '0' when ((abus(19 downto 13)="0000000") AND iom='0') else '1';
we_text <= '1' when (cstextram='0' AND wrn='0') else '0';
-- VGA Buffer 32Kbyte, A0000 to A7FFF
csdispram <= '0' when ((abus(19 downto 15)="10100") AND iom='0') else '1'; we_disp <= '1' when (csdispram='0' AND wrn='0') else '0';
-- External Memory 1MByte - Bootstrap ROM - Program RAM - VGA Buffer
csramn <= '0' when (csrom='0' AND cstextram='1' AND csdispram='1' AND cskey='1' AND iom='0') else '1';
-- HDL Embedded Text Block 8 tristate2
-- eb2 2
PROCESS (wrn,dbus_out_cpu)
BEGIN
CASE wrn IS
when '0' => fse_d<= dbus_out_cpu & dbus_out_cpu & dbus_out_cpu & dbus_out_cpu; -- drive PORT
when others => fse_d<= (others => 'Z') after 10 ns;
END CASE;
END PROCESS;
PROCESS (abus, fse_d)
BEGIN
CASE abus(1 downto 0) IS
when "00" => dbus_ext <= fse_d(7 downto 0);
when "01" => dbus_ext <= fse_d(15 downto 8);
when "10" => dbus_ext <= fse_d(23 downto 16);
when others => dbus_ext <= fse_d(31 downto 24);
END CASE;
END PROCESS;
-- ModuleWare code(v1.5) for instance 'U_4' of 'gnd'
intr <= '0';
-- ModuleWare code(v1.5) for instance 'U_5' of 'gnd'
test <= '0';
-- Instance PORT mappings.
U_0 : cpu86
PORT MAP(
clk => clkout,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
step_sw => proc_error,
test => test,
abus => abus,
biu_error => biu_error,
dbus_out => dbus_out_cpu,
inta => OPEN,
iom => iom,
lock => lock,
proc_error => proc_error,
rdn => rdn,
resoutn => resetn,
step_mux => step_mux,
step_on => step_on,
txmon => txmon,
wran => wran,
wrn => wrn
);
U_1 : superio_top
GENERIC MAP (
COM_DIVIDER => 52,
TMR_DIVIDER91 => 359256,
UART2_G => TRUE
)
PORT MAP (
abus => abus(15 DOWNTO 0),
clk => clkout,
dbusin => dbus_out_cpu,
inport => inport,
iom => iom,
rdn => rdn,
resetn => resetn,
rx1 => rxd1,
rx2 => rxd2,
wrn => wrn,
dbusout => dbus_io,
outport => outport,
pulse182 => OPEN,
tx1 => txd1,
tx2 => tx2
);
U_2 : embedded_rom
PORT MAP (
a => abus(7 DOWNTO 0),
clk => clkout,
spo => dbus_rom
);
U_5: textram
PORT MAP(
clk => clkout,
addr => abus(12 DOWNTO 0),
din => dbus_out_cpu,
dout => dbus_text_ram,
we => we_text
); U_6: disp_ram
PORT MAP(
addra => abus(14 DOWNTO 0),
addrb => disp_addr,
clka => clkout,
clkb => clkout,
dina => dbus_out_cpu,
douta => dbus_disp_ram,
doutb => disp_dout,
wea => we_disp ); U_7: disp
PORT MAP(
reset => cpu_resetn,
clk => clkout,
addr_out => disp_addr,
data_in => disp_dout,
red => red,
green => green,
blue => blue,
Hsync => Hsync,
Vsync => Vsync
); U_8: myclock
PORT MAP(
CLKIN_IN => clk,
RST_IN => '0',
CLKDV_OUT => clkout,
CLK0_OUT => open,
LOCKED_OUT => OPEN );
END struct;⌨️ 快捷键说明
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