代码搜索结果

-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_v

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -----实体count10的说明 ENTITY COUNT10 IS PORT(CLK:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); SEL:OUT STD_

Logic Redirect sample code

Logic Forward sample code

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD IS PORT( DD:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ST,EOC:IN STD_LOGIC; ALE,STA:OUT STD_LOGIC; OE,ADDA:OUT STD_LOGIC; QQ:OUT STD_LOGIC_VECTOR(7

library ieee; use ieee.std_logic_1164.all; entity encode is port( d: in std_logic_vector(7 downto 0); ein : in std_logic; a0n,a1n,a2n,gsn,eon : out std_logic); end encode; architecture beh

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY t10 IS PORT( cpd,cps : IN STD_LOGIC; lr,lg,ly : OUT STD_LOGIC_VECTOR(4 downto 1); d : OUT STD_LOGIC_VECTOR(6 downto 0); sel : OUT STD_

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY tbjsb IS PORT( cp : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR(2 downto 0)); END tbjsb; ARCHITECTURE a OF tbjsb IS COMPONENT JKFF PORT (j

--********************************************* -- Listing A.6 --********************************************* library ieee; use ieee.std_logic_1164.all; entity decoder2 is port( a: in

-- Listing 13.8 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity m100_counter is port( clk, reset: in std_logic; d_inc, d_clr: in std_logic; dig