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_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s18 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ramb16_s36 is
generic(
cds_action : string := "ignore";
init : integer := 0;
srval : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v1_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v2_0 is
generic(
c_enable_rlocs : integer := 1;
c_encode_type : integer := 0;
c_force_code_disp: integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v2_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v1_0 is
generic(
c_enable_rlocs : integer := 1;
c_encode_type : integer := 0;
c_force_code_disp: integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decode_8b10b_v3_0 is
generic(
c_decode_type : integer := 1;
c_enable_rlocs : integer := 0;
c_has_bports : integer :=
uc_interface.vhd
-- File: uC_interface.vhd
--
-- Author: Jennifer Jenkins
-- Philips Semiconductor
-- Purpose: Description of an interface with a ucontroller/uprocessor
-- (i.e. Motorola 68000)
dcm_phase_shift.vhd
-------------------------------------------------------------------------------
-- Digital Clock Manager (DCM) --
-- DCM in Phase Shifter mode
suocunf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY suocunf IS
PORT(
IN2:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
IN3:IN