dcm_phase_shift.vhd

Xilinx Ise 官方源代码盘 第四章

-------------------------------------------------------------------------------
--                       Digital Clock Manager (DCM)                         --
--           DCM in Phase Shifter mode instanciation using Synplify          --
-------------------------------------------------------------------------------
--
-- GENERAL:
-- Synplify (with attribute specification) can infer Virtex-II DCM 
--   cells for clock de-skew purposes. For more advanced features instanciation
--   is required.
--
-- DCM resources: 
--   * See Virtex-II Handbook and "DC and Switching Characteristics" of the 
--       data sheet for more details.
--   * Digital Clock Manager (DCM) provides multiple functions. Functionalities
--       are not exclusive. Combinations are possible.
--      - Clock Delay Locked Loop (DLL): DCM generates new system clocks
--          (internal or external to the FPGA), that are phase-aligned to the
--          input clock. (Clock De-skew)
--      - Digital Frequency Synthesizer (DFS): DCM generates a wide range of 
--          output clock frequencies, performing a flexible input clock 
--          multiplication or division. (Frequency Synthesis)
--      - Digital Phase Shifter (DPS): DCM provides both coarse and fine-grained
--          phase shifting with dynamic phase shift control, between DCM input
--          and output clocks. (Phase Shifting)
--          
-- NOTES:
--     * Synplify infers a DCM in mode Delay Locked Loop (DLL) when input clock
--          signal is tagged with attribute "xc_clockbuftype" set to "BUFGDLL".
--          (Clock De-skew)
--     * For other features instanciattion is required
-- Log file message:
--     * Resource Usage Report section (Cell usage)
--          DCM             1 use
-------------------------------------------------------------------------------
-- Example: Phase shifter mode DCM instanciation (clk is dynamically phased 
--     shifted compared to CLKIN)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   --signed arithmetics library

entity dcm_phase_shift is
  port ( clk33_board              : in    std_logic;
         rst_dll                  : in    std_logic;
         ce                       : in    std_logic;
         pulse_psen               : in    std_logic;
         psincdec                 : in    std_logic;
         a                        : in    std_logic_vector(15 downto 0);
         b                        : in    std_logic_vector(15 downto 0);
         p                        : out   std_logic_vector(31 downto 0);
         locked                   : out   std_logic;
         psdone                   : out   std_logic );
end entity dcm_phase_shift;

architecture structural of dcm_phase_shift is
  signal clk33_ibufg : std_logic;
  signal clk0_dcm    : std_logic;
  signal clk         : std_logic;

  component IBUFG
    port ( I : in  std_logic;
           O : out std_logic );
  end component;

  component BUFG
    port ( I : in  std_logic;
           O : out std_logic );
  end component;

  attribute DLL_FREQUENCY_MODE : string;
  attribute CLKOUT_PHASE_SHIFT : string;
  attribute PHASE_SHIFT        : integer;
  attribute STARTUP_WAIT       : string;

  attribute DLL_FREQUENCY_MODE of my_dcm: label is "LOW";      -- Frequency mode selection
  attribute CLKOUT_PHASE_SHIFT of my_dcm: label is "VARIABLE"; -- Enable variable output clock phase shifting
  attribute PHASE_SHIFT        of my_dcm: label is -5;         -- Default phase shift on startup or reset
  attribute STARTUP_WAIT       of my_dcm: label is "TRUE";

  component DCM
    port ( CLKIN    : in  std_logic;
           CLKFB    : in  std_logic;
           DSSEN    : in  std_logic;
           PSINCDEC : in  std_logic;
           PSEN     : in  std_logic;
           PSCLK    : in  std_logic;
           RST      : in  std_logic;
           CLK0     : out std_logic;
           CLK90    : out std_logic;
           CLK180   : out std_logic;
           CLK270   : out std_logic;
           CLK2X    : out std_logic;
           CLK2X180 : out std_logic;
           CLKDV    : out std_logic;
           CLKFX    : out std_logic;
           CLKFX180 : out std_logic;
           LOCKED   : out std_logic;
           PSDONE   : out std_logic;
           STATUS   : out std_logic_vector(7 downto 0) );
  end component;

begin

  clk_pad_ibufg : IBUFG
    port map ( I => clk33_board,
               O => clk33_ibufg );

  my_dcm: DCM
    port map ( CLKIN    => clk33_ibufg,
               CLKFB    => clk,
               DSSEN    => '0',
               PSINCDEC => psincdec,
               PSEN     => pulse_psen,
               PSCLK    => clk33_ibufg,
               RST      => rst_dll,
               CLK0     => clk0_dcm,
               CLK90    => open,
               CLK180   => open,
               CLK270   => open,
               CLK2X    => open,
               CLK2X180 => open,
               CLKDV    => open,
               CLKFX    => open,
               CLKFX180 => open,
               LOCKED   => locked,
               PSDONE   => psdone,
               STATUS   => open );

  dcm_output_buffer : BUFG        -- serve as feedback and clock distribution
    port map ( I => clk0_dcm,     
               O => clk );


-- other code
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
          p <= a * b;
       end if;
    end if;
  end process;

end architecture structural;