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Logic Analyzer 的代码
dds.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
DA_CLK : OUT
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
cpldbus51_tb.vhd
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
entity cpldbus51_tb is
end cpldbus51_tb;
architecture TB_ARCHITECTURE of cpldbus51_tb is
-- Component declaration o
cop2000.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COP2000 IS
GENERIC(
ALL_ZERO : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000"; -- 十六位机
INT_ENTER:
pulsef.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY PULSEf IS --脉冲形成器
port(clk4,bj: in std_logic;
out4: out std_
bijiaoqi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bijiaoqi IS
port(a1,a2,b1,b2: in std_logic;
m: out std_logic);
end entity bijiaoqi;
architecture fm1 of bijiaoqi is
signal zdf1,zdf2: s
fenpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
outp0,outp1:out std_logic);
end fenpin;
architecture bh of fenpin is
jiafaqi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY jiafaqi IS
port(a: in std_logic;
o1,o2: out std_logic);
end entity jiafaqi;
architecture fh1 of jiafaqi is
begin
o1
pre.vhd
--
-- pre.vhd
--
-- Cordic pre-processing block
--
--
-- step 1: determine quadrant and generate absolute value of X and Y
-- Q1: Xnegative
-- Q2: Ynegative
--
-- step 2: swap X and Y values if Y>X