pulsef.vhd

应用vhdl语言进行加法器的设计

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY  PULSEf IS                --脉冲形成器
port(clk4,bj: in std_logic;
     out4: out std_logic);
end entity PULSEf;
ARCHITECTURE MM OF PULSEf IS
COMPONENT djhand
PORT(a,b:IN STD_LOGIC;
     O: OUT STD_LOGIC);
END COMPONENT djhand;
COMPONENT djhnot
 PORT(a: IN STD_LOGIC;
      o: OUT STD_LOGIC);
END COMPONENT djhnot;
COMPONENT djhlatch
PORT(d,ena: IN STD_LOGIC;
     q1: OUT STD_LOGIC);
END COMPONENT djhlatch;
SIGNAL g,e:std_logic;
begin
m1: djhand port map(a=>bj,b=>e,o=>out4);
m2:djhnot port map(a=>g,o=>e);
m3: djhlatch port map(d=>bj,q1=>g,ena=>clk4);
END ARCHITECTURE MM; 

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY djhnot IS              --非门
	PORT(a:IN std_logic;
		 o: OUT std_logic);
END entity djhnot;
ARCHITECTURE one OF djhnot IS 
begin
o<=NOT a;
END architecture one;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY djhlatch IS                        --D触发器
	PORT(D,ena	: IN std_logic;
		 q1: OUT std_logic);
END entity djhlatch;
ARCHITECTURE one OF djhlatch IS
signal sig_save: std_logic;
BEGIN
  process(d,ena)
begin
 if ena'event and ena='1' then
   sig_save<=d;
 end if;
 q1<=sig_save; 
end process;
END architecture one;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY djhand IS
	PORT(a,b: IN std_logic;           --与门
		 o:OUT std_logic);
END entity djhand;
ARCHITECTURE one OF djhand IS 
begin
 o<=a AND b;
END architecture one;