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找到约 10,000 项符合
Logic Analyzer 的代码
control.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CONTROL IS
PORT( CLK,RESET,SET : IN STD_LOGIC;
ADIN : IN STD_LOGIC_
uart_clock.vhd
--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KC
pico_test.vhd
-----------------------------------------------------------------
--
-- Pico_test.vhd
--
-- Author: Nial Stewart, Nial Stewart Developments Ltd.
-- www.nialstewart.co.uk
-- J
kcpsm.vhd
-- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices
--
-- Version : 1.00c
-- Version Date : 14th August 2002
--
-- Start of design entry : 2nd July 2002
--
-- K
m10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity m10 is
port(
clk,reset:in std_logic;
cout:out std_logic_vector(3 downto 0);
c
lock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lock is
port(
in0,in1,in2,in3:in std_logic_vector(3 downto 0);
clk : in std_logic;
out0,out1,out2,out3:out std_logic_vector(3 downto 0)
ssram_rtl.vhd
-------------------------------------------------------------------------------
-- --
-- AES86 - VHDL 128bits AES IP Core
shiftamountreg.vhd
--****************************************************************************************************
-- Shifter control register for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modifi
memoryremapper.vhd
--****************************************************************************************************
-- Memory remapper for ARM core simualtion
-- Designed by Ruslan Lepetenok
-- Modified 26.12.2
abusmultiplexer.vhd
--****************************************************************************************************
-- A bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1