ssram_rtl.vhd

VHDL to System C translator

-------------------------------------------------------------------------------
--                                                                           --
--  AES86 - VHDL 128bits AES IP Core                                         --
--  Copyright (C) 2005-2007 HT-LAB                                           --
--                                                                           --
--  Contact/Feedback : http://www.ht-lab.com/feedback.htm                    --
--  Web: http://www.ht-lab.com                                               --
--                                                                           --
--  AES86 is released as open-source under the GNU GPL license. This means   --
--  that designs based on AES86 must be distributed in full source code      --
--  under the same license. Contact HT-Lab for commercial applications where --
--  source-code distribution is not desirable.                               --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
--                                                                           --
--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
--                                                                           --
--  Full details of the license can be found in the file "copying.txt".      --
--                                                                           --
--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Architecture AES_Web_lib.AES_cpu_top_tb.symbol
--
-- Created: by - Hans 22/05/2005
-------------------------------------------------------------------------------
-- Actel Synchronous Memory
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity ssram is
   port( 
      clk     : in     std_logic;
      din128  : in     std_logic_vector (127 downto 0);
      addr    : in     std_logic_vector (3 downto 0);
      we      : in     std_logic;
      dout128 : out    std_logic_vector (127 downto 0)
   );
end ssram ;


architecture rtl of ssram is

type mem_type is array (15 downto 0) of std_logic_vector(127 downto 0) ;
signal mem : mem_type;

begin

singleport : process (clk)
    begin
        if (clk'event and clk = '1') then
            if (we = '1') then
                mem(conv_integer(addr)) <= din128;
            else
                dout128 <= mem(conv_integer(addr));
            end if ;
        end if;
end process singleport;

end architecture rtl;