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找到约 10,000 项符合
Logic Analyzer 的代码
my_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component div_clock
port(clk: in std_logic;
f50hz: out std_logic;
f10hz: out std_logic;-- 5Hz output signal
f5hz: out std_
counter24.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER24 IS
PORT(
CP : IN STD_LOGIC;
BIN : OUT STD_LOGIC_VECTOR (5 DOWN
bwcfq.txt
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY part6 IS
PORT(DATAA,DATAB:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RESULT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END
dividend4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dividend4 is
port(dividend_in:in std_logic_vector(7 downto 0);
divisor:in std_lo
m4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m4 is
port(clk :in std_logic;
set :in std_logic;
qin :in std_logic_vector(1 downto 0);
q :buf
addm4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addm4 is
port(clk :in std_logic;
set :in std_logic;
qin :in std_logic_vector(1 downto 0);
q :
danxiangm16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity danxiangm16 is
port(clk :in std_logic;
zhishu :in std_logic;
din :in std_logic_vector(3 downto 0)
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --3.125MHZ FROM div16 Module
kang.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package kang is
component tsb is
Port ( clk : in std_logic;
data_in : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(3 downto 0);
piso.vhd
library ieee;
use ieee.std_logic_1164.all;
entity piso is
port (load : in std_logic;
clock:in std_logic;
po:out std_logic_vector(31 downto 0);
sI:IN std_logic;
en