danxiangm16.vhd

此为一用VHDL编写的硬件游戏程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity danxiangm16 is
port(clk :in std_logic;
     zhishu :in std_logic;
     din   :in std_logic_vector(3 downto 0);
     do    :buffer std_logic_vector(3 downto 0);
     iffull :out std_logic);
end danxiangm16;
architecture behave of danxiangm16 is
begin
  process(clk)
   begin
     if(rising_edge(clk))then
         if(zhishu='1')then
             do<=din;
          elsif(din="1111")then
            iffull<='1';
            do<="0000";
          else
             iffull<='0';
             do<=do+1;
          end if;
       end if;
    end process;
end behave;