m4add_jian.vhd

来自「此为一用VHDL编写的硬件游戏程序」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m4add_jian is
port(clk :in std_logic;
     add :in std_logic;
     jian :in std_logic;
     set  :in std_logic;
     win  :in std_logic_vector(1 downto 0);
     weizhi :buffer std_logic_vector(1 downto 0));
end m4add_jian;
architecture behave of m4add_jian is
signal temp :std_logic_vector(1 downto 0);
begin
    temp<=add&jian;
   process(clk)
   begin
      if(rising_edge(clk))then
         if(set='1')then
              weizhi<=win;
         else
            case temp is
               when "01"=>if(weizhi="10" or weizhi="11")then
                          weizhi<=weizhi-1;
                          else weizhi<=weizhi;
                          end if;
               when "10"=>if(weizhi="01" or weizhi="10")then 
                            weizhi<=weizhi+1;
                            else
                             weizhi<=weizhi;
                            end if;
               when others=>weizhi<=weizhi;
             end case;
         end if;
       end if;
end process;
end behave;