bwcfq.txt

纯组合逻辑构成的乘法器虽然工作速度比较快

library ieee; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY part6 IS 
PORT(DATAA,DATAB:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 
RESULT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); 
END part6; 
architecture BEHAVIOR OF part6 IS 
COMPONENT MULTIPLIER_4BIT 
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
END COMPONENT; 
SIGNAL SUM12H,SUM12L:STD_LOGIC_VECTOR(11 DOWNTO 0); 

SIGNAL SIN3,SIN2,SIN1,SIN0:STD_LOGIC_VECTOR(7 DOWNTO 0); 
BEGIN 
UNIT1:MULTIPLIER_4BIT PORT MAP(A=>DATAA(3 DOWNTO 0),B=>DATAB(3 DOWNTO 0),P=>SIN0); 
UNIT2:MULTIPLIER_4BIT PORT MAP(A=>DATAA(7 DOWNTO 4),B=>DATAB(3 DOWNTO 0),P=>SIN1); 
UNIT3:MULTIPLIER_4BIT PORT MAP(A=>DATAA(3 DOWNTO 0),B=>DATAB(7 DOWNTO 4),P=>SIN2); 
UNIT4:MULTIPLIER_4BIT PORT MAP(A=>DATAA(7 DOWNTO 4),B=>DATAB(7 DOWNTO 4),P=>SIN3); 
SUM12L<=SIN1&"0000"+SIN0; 
SUM12H<=SIN3&"0000"+SIN2; 
RESULT<=SUM12H&"0000"+SUM12L; 

END BEHAVIOR; 

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY MULTIPLIER_4BIT IS 
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); 
END MULTIPLIER_4BIT; 
ARCHITECTURE BEHAVIOR OF MULTIPLIER_4BIT IS 
COMPONENT ADDER_1BIT 
PORT(DA,DB,CI:IN STD_LOGIC; 
S,CO:OUT STD_LOGIC); 
END COMPONENT; 
SIGNAL C1,C2,C3:STD_LOGIC_VECTOR(3 DOWNTO 0); 
SIGNAL S1,S2:STD_LOGIC_VECTOR(2 DOWNTO 0); 
BEGIN 
FA1:ADDER_1BIT PORT MAP(DA=>A(1) AND B(0),DB=>A(0) AND B(1),CI=>'0',S=>P(1),CO=>C1(0)); 
FA2:ADDER_1BIT PORT MAP(DA=>A(2) AND B(0),DB=>A(1) AND B(1),CI=>C1(0),S=>S1(0),CO=>C1(1)); 
FA3:ADDER_1BIT PORT MAP(DA=>A(3) AND B(0),DB=>A(2) AND B(1),CI=>C1(1),S=>S1(1),CO=>C1(2)); 
FA4:ADDER_1BIT PORT MAP(DA=>'0',DB=>A(3) AND B(1),CI=>C1(2),S=>S1(2),CO=>C1(3)); 
FA5:ADDER_1BIT PORT MAP(DA=>S1(0),DB=>A(0) AND B(2),CI=>'0',S=>P(2),CO=>C2(0)); 
FA6:ADDER_1BIT PORT MAP(DA=>S1(1),DB=>A(1) AND B(2),CI=>C2(0),S=>S2(0),CO=>C2(1)); 
FA7:ADDER_1BIT PORT MAP(DA=>S1(2),DB=>A(2) AND B(2),CI=>C2(1),S=>S2(1),CO=>C2(2)); 
FA8:ADDER_1BIT PORT MAP(DA=>C1(3),DB=>A(3) AND B(2),CI=>C2(2),S=>S2(2),CO=>C2(3)); 
FA9:ADDER_1BIT PORT MAP(DA=>S2(0),DB=>A(0) AND B(3),CI=>'0',S=>P(3),CO=>C3(0)); 
FA10:ADDER_1BIT PORT MAP(DA=>S2(1),DB=>A(1) AND B(3),CI=>C3(0),S=>P(4),CO=>C3(1)); 
FA11:ADDER_1BIT PORT MAP(DA=>S2(2),DB=>A(2) AND B(3),CI=>C3(1),S=>P(5),CO=>C3(2)); 
FA12:ADDER_1BIT PORT MAP(DA=>C2(3),DB=>A(3) AND B(3),CI=>C3(2),S=>P(6),CO=>P(7)); 
P(0)<=A(0) AND B(0); 

END BEHAVIOR; 

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY ADDER_1BIT IS 
PORT(DA,DB,CI:IN STD_LOGIC; 
S,CO:OUT STD_LOGIC); 
END ADDER_1BIT; 
ARCHITECTURE BEHAVIOR OF ADDER_1BIT IS 
SIGNAL SIN:STD_LOGIC_VECTOR(1 DOWNTO 0); 
BEGIN 
SIN<='0'&DA+DB+CI; 
S<=SIN(0); 
CO<=SIN(1); 
END BEHAVIOR;