📄 kang.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
package kang is
component tsb is
Port ( clk : in std_logic;
data_in : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(3 downto 0);
first_oct : out std_logic );
end component;
component tap_lut is
Port ( clk : in std_logic;
write_en : in std_logic;
Write_Data : in std_logic_vector(14 downto 0);
lut_input : in std_logic_vector(3 downto 0);
lut_output : out std_logic_vector(14 downto 0) );
end component;
component mux_reg15 is
Port ( clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
mux_in15a : in std_logic_vector(14 downto 0);
mux_in15b : in std_logic_vector(14 downto 0);
mux_out15 : out std_logic_vector(14 downto 0) );
end component;
component pp_adder is
Port ( clk : in std_logic;
rst : in std_logic;
f_oct : in std_logic;
valid : out std_logic;
input : in std_logic_vector(14 downto 0);
output : out std_logic_vector(23 downto 0) );
end component;
end kang;
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