tap_lut.vhd

来自「自适应滤波器adaptive的vhdl实现的源代码。」· VHDL 代码 · 共 33 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tap_lut is
Port ( clk : in std_logic;
write_en : in std_logic;
Write_Data : in std_logic_vector(14 downto 0);
lut_input : in std_logic_vector(3 downto 0);
lut_output : out std_logic_vector(14 downto 0) );
end;

-- tap_lut Component
architecture Behavioral of tap_lut is
type lut_array is array (0 to 15) of std_logic_vector(14 downto 0);
signal lut_contents : lut_array;
begin
process(clk, write_en)
variable addr : integer range 0 to 15;

begin
if clk'event and clk = '1' then
addr := CONV_INTEGER(lut_input);
if write_en = '1' then
lut_contents(addr) <= Write_Data;
lut_output <= (others => '0');
else
lut_output <= lut_contents(addr);
end if;
end if;
end process;
end Behavioral;