counter24.vhd

自己做的vhdl课程设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER24 IS
PORT(
CP : IN  STD_LOGIC;   
BIN : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);  
S    : IN  STD_LOGIC;        
CLR  : IN  STD_LOGIC;    
EC   : IN  STD_LOGIC;       
CY24 : OUT STD_LOGIC       
);
END COUNTER24;

ARCHITECTURE a OF COUNTER24 IS
SIGNAL Q : STD_LOGIC_VECTOR (4 DOWNTO 0) ;
SIGNAL RST, DLY : STD_LOGIC;
BEGIN
PROCESS (CP,RST)     
BEGIN
IF RST = '1' THEN
Q <= "00000";  
ELSIF CP'event AND CP = '1' THEN
DLY <= Q(4);
IF EC = '1' THEN
Q <= Q+1;    
END IF; 
END IF;
END PROCESS;
CY24 <= NOT Q(4) AND DLY;RST <= '1' WHEN Q=24 OR CLR='1' ELSE       
   '0';
BIN <= ('0' & Q) WHEN S = '1' ELSE    
   "000000";
END a;