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Logic Analyzer 的代码
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-- --
-- Copyright(c) Hynix Semiconductor Inc. 2005. All rights
crc8.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
wogodiv.vhd
--成功作品；以后总结
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY wogodiv IS
PORT(
CLK:IN STD_LOGIC;
outclk:out std_logic);
end wogodiv;
ARCHITECTURE meter OF wogodiv
counter10.vhd
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
Port ( clk :
counter24.vhd
--文件名：counter24.vhd。
--功能：24进制计数器。
--最后修改日期：2008.04.26
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
Port (
ps7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps7 is
port(clk:in std_logic;
load:in std_logic;
q:out std_logic;
count1:out std_logic_vector(7 downto 0) );
ps7.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps7 is
port(clk:in std_logic;
load:in std_logic;
q:out std_logic;
count1:out std_logic_vector(8 downto 0) );
nia.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nia is
port (clk, ena: in std_logic;
dn, qn: out std_logic_vector(3 downto 0);
yf: out std_
v1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity v1 is
port(cp,intr:in std_logic;
da:in std_logic_vector(7 downto 0);
-- ad:out std_logic_vector(7
v.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity v is
port(cp,intr:in std_logic;
da:in std_logic_vector(7 downto 0);
-- ad:out std_logic_vector(7