v1.vhd

交流电压表相应的VHDL代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity v1 is
  port(cp,intr:in std_logic;
       da:in std_logic_vector(7 downto 0);
--     ad:out std_logic_vector(7 downto 0);
       uled:out std_logic_vector(2 downto 0);
       rd:out   std_logic;  
       seg:out std_logic_vector(6 downto 0);
       ledh:out std_logic_vector(0 to 3)       );
end v1;

architecture rtl of v1 is
component c_1000 
  port(clk:in std_logic;
        co:out std_logic);
end component;
component c_20 
  port(clk:in std_logic;
        co:out std_logic);
end component;
component counter_600 
  port(rd,intr:in std_logic;
       da:in std_logic_vector(7 downto 0);
       d1,d2,d3:out std_logic_vector(3 downto 0));
end component;
component disp 
  port(clk:in std_logic;
        d1,d2,d3:in std_logic_vector(3 downto 0);        
        seg:out std_logic_vector(6 downto 0);
        ledh:out std_logic_vector(0 to 3)        );
end component;

   signal clk1,clk2,clk3,clk4:std_logic;
   signal d1,d2,d3:std_logic_vector(3 downto 0);  
begin
 uled<="000";
--ad<="11111111";
  rd<=clk3;
  u1:c_1000 port map(cp,clk1); 
  u2:c_20 port map(clk1,clk2); 
  u3:c_20 port map(clk2,clk3);
  u4:counter_600 port map(clk4,intr,da,d1,d2,d3);
  u5:disp port map(clk3,d1,d2,d3,seg,ledh);
  u6:c_20 port map(clk3,clk4);
 end rtl;


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