nia.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nia is
port (clk, ena: in std_logic;
        dn, qn: out std_logic_vector(3 downto 0);
            yf: out std_logic);
end nia;
architecture one of nia is
    signal dnt, qnt: std_logic_vector(3 downto 0);
    signal yfi:std_logic_vector(1 downto 0);
begin
 process (clk,ena,dnt,qnt,yfi)
   begin
   if ena='0' then
     dnt<="0000";
     qnt<="0000";
     yfi<="00";
     yf<='1';
   elsif rising_edge(clk) then
      if qnt="1001" and dnt="1001" then qnt<="0000"; dnt<="0000"; yfi<="00";               
      elsif dnt<"1001" then dnt<=dnt+1; yfi<=yfi+1;
         elsif dnt="1001" then qnt<=qnt+1; dnt<="0000"; yfi<=yfi+1;
      end if;
      if yfi="11" then yf<='1';
      else yf<='0';
      end if;
   end if;
 dn<=dnt;
 qn<=qnt;
 end process;
end one;