crc8.vhd

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity crc8 is
   port(clk_25m : in std_logic;
   	   data_ld : in std_logic;
   	   dcrci:in std_logic_vector(39 downto 0);
	   dcrco:out std_logic_vector(46 downto 0);
	   crcfini:out std_logic
	   );
end crc8;

architecture Beh of crc8 is
   constant gen_poly:std_logic_vector(7 downto 0):="10001001"; ------CRC校验生成多项式
   signal dtemp:std_logic_vector(46 downto 0);
   signal sdatam:std_logic_vector(39 downto 0);
   signal rcnt :integer range 0 to 41;
   signal st :std_logic:='0';	        -------
begin

---------------------CRC校验码生成模块(发送)----------------------
   process(clk_25m)
      variable crcvar :std_logic_vector(7 downto 0);
   begin
	if clk_25m'event and clk_25m='1' then
			if st='0' and data_ld='1' then  
				dtemp<=dcrci&b"0000000"; 
				sdatam<=dcrci;
				rcnt<=0;
				st<='1';
			elsif st='1' and rcnt<40 then
				rcnt<=rcnt+1;
				if dtemp(46)='1' then
					crcvar:=dtemp(46 downto 39) xor gen_poly;
					dtemp<=crcvar(6 downto 0) & dtemp(38 downto 0) & '0';
				else dtemp<=dtemp(45 downto 0) &'0';
				end if;
			elsif st='1' and rcnt=40 then
				dcrco<=sdatam & dtemp(46 downto 40);
				crcfini<='1';
				rcnt<=rcnt+1;
			elsif rcnt=41 then
				crcfini<='0';
				st<='0';
			end if;
	end if;				   	  
   end process;
---------------------CRC校验检错模块(接收)-------------------
--   process(clk)
--   begin
--   end process;
end Beh;