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ddr 2 接口读写测试模块 ddr 2 接口读写测试模块

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--                                                                  --
-- Copyright(c) Hynix Semiconductor Inc. 2005. All rights reserved. --
--                                                                  --
--       VHDL Simulation Model of 512M DDR2 Device, rev.0.1         --
--                   (4 Banks x 16M x 8 I/Os)                       --
--                                                                  --
--                    PART : HY5PS12821BF                           --
--                                                                  --
--                     DATE : 2005. 6. 20                           --
--                                                                  --
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--
-- * verification tool : ModelSim SE PLUS 6.0
--
-- * speed bins :
-- B400B = DDR2-400B 3-3-3
-- B533C = DDR2-533C 4-4-4
-- B667D = DDR2-667D 5-5-5
-- B667C = DDR2-667C 4-4-4
-- B800E = DDR2-800E 6-6-6
-- B800D = DDR2-800D 5-5-5
--

The device pin configuration is as follows, (in VHDL format)


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USE     STD.textio.all;
LIBRARY IEEE;
USE     IEEE.STD_LOGIC_1164.all;
USE     IEEE.STD_LOGIC_TEXTIO.all;
USE     WORK.HY5PS12821BF_PACK.all;
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component HY5PS12821BF
  generic (
     TimingCheckFlag : boolean       := TRUE;
     PUSCheckFlag    : boolean       := FALSE;
     Part_Number     : PART_NUM_TYPE := B667D);
  port ( CLK     : in    std_logic ;
         CLKB    : in    std_logic ;
         CKE     : in    std_logic ;
         CSB     : in    std_logic ;
         RASB    : in    std_logic ;
         CASB    : in    std_logic ;
         WEB     : in    std_logic ;
         BA      : in    std_logic_vector (1  downto 0) ;
         ADDR    : in    std_logic_vector (13 downto 0) ;
         
         RDQSB   :   out std_logic ;
         DM_RDQS : inout std_logic := 'Z' ;
         DQS     : inout std_logic := 'Z' ;
         DQSB    : inout std_logic := 'Z' ;
         DQ      : inout std_logic_vector (7  downto 0) := (others => 'Z') ) ;
End component HY5PS12821BF;
 
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-> The simulation time unit must be set to 'PS'(picosecond).
-> If you don't use power-up sequence, the first command must be inputted 
   after an elapse of 2 clock cycles.(except 'NOP' and 'DSEL')