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Logic Analyzer 的代码
txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
receive_top.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:17:58 12/01/2007
-- Design Name:
-- Module Name: rece
addbcd_4.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(
addbcd_8.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity eecadd_8 is
port (cin8:in std_logic;
a:in std_logic_vector(7 downto 0);
fft.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
eecadd_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(
dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
qichewendengvhdlsheji.txt
0571-86919140
汽车尾灯VHDL设计
标签/分类：
1．系统设计要求
用6个发光管模拟6个汽车尾灯（左右各3个），用4个开关作为汽车控制信号,分别为：左拐、右拐、故障和刹车。
车匀速行驶时，6个汽车尾灯全灭；右拐时，车右边3个尾灯从左至右顺序亮灭；左拐时，车左边3个尾灯从右至左顺序亮灭；故障时车6个尾灯一起明灭闪烁；刹车时，6个尾灯全亮
...