addbcd_4.txt

此程序采用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
    b: in std_logic_vector(3 downto 0);
    cin:in std_logic;
    bcdout: out std_logic_vector(3 downto 0);
    cout:out std_logic );
end eecadd_4;
architecture arch of eecadd_4 is
  signal co:std_logic_vector(3 downto 0);
  signal y,s,d:std_logic_vector(3 downto 0);
  signal e:std_logic_vector(4 downto 0);
  signal f:std_logic;
  begin
     y(0)<=a(0)xor b(0)xor cin;
     co(0)<=(a(0)and b(0))or(b(0)and cin)or(a(0)and cin);
       gen:for I in 1 to 3 generate
          y(I)<=a(I)xor b(I)xor co(I-1);
          co(I)<=(co(I-1)and a(I)) or (co(I-1)and b(I))or (a(I)and b(I));
end generate;
     e<=y&co(3);
process(a,b,y,d)
	begin
		case e is
         when"00000"=>d<="0000";
         when"00010"=>d<="0001";
         when"00100"=>d<="0010";
         when"00110"=>d<="0011";
         when"01000"=>d<="0100";
         when"01010"=>d<="0101";
         when"01100"=>d<="0110";
         when"01110"=>d<="0111";
         when"10000"=>d<="1000";
         when"10010"=>d<="1001";
         when"10100"=>d<="0000";
         when"10110"=>d<="0001";
	     when"11000"=>d<="0010";
	     when"11010"=>d<="0011";
	     when"11100"=>d<="0100";
	     when"11110"=>d<="0101";
	     when"00001"=>d<="0110";
	     when"00011"=>d<="0111";
	     when"00101"=>d<="1000";
	     when"00111"=>d<="1001";
         when others =>d<=y;
         end case;      
    end process;
         s<=y;
    f<='1' when s="1010" else
       '1' when s="1011" else
       '1' when s="1100" else
       '1' when s="1101" else
       '1' when s="1110" else
       '1' when s="1111" else
       '0';
    cout<=f or co(3);          
    bcdout<=d;
end arch;