addbcd_8.txt

此程序采用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity eecadd_8 is
port (cin8:in std_logic;
      a:in std_logic_vector(7 downto 0);
      b:in std_logic_vector(7 downto 0);
      cout8:out std_logic;
      c:out std_logic_vector(7 downto 0));
end eecadd_8;
architecture bhv of eecadd_8 is
component eecadd_4
  port(a,b:in std_logic_vector(3 downto 0);
       cin:in std_logic;
       bcdout:out std_logic_vector(3 downto 0);
       cout:out std_logic);
end component;
      signal d:std_logic_vector(7 downto 0);
      signal e:std_logic_vector(1 downto 0);
begin
u0: eecadd_4 port map(a(3 downto 0),b(3 downto 0),cin8,d(3 downto 0),e(0));
u1: eecadd_4 port map(a(7 downto 4),b(7 downto 4),e(0),d(7 downto 4),e(1));
c<=d;
cout8<=e(1);
end bhv;