receive_top.vhd

编码器系统

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:17:58 12/01/2007 
-- Design Name: 
-- Module Name:    receive_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity receive_top is
port	(
			clk : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			dsp_are_n : in std_logic;
			addr_r : in std_logic_vector(4 downto 0);
			data_out : out std_logic_vector(7 downto 0)
		);
end receive_top;

architecture Behavioral of receive_top is

component receiver is
port	(
			clk16x : in std_logic;
			reset : in std_logic;
			rx : in std_logic;
			read : out std_logic;
			data_out : out std_logic_vector(7 downto 0)
		);
end component;

component dpram_rx
port	(
			addra : in std_logic_vector(4 downto 0);
			addrb : in std_logic_vector(4 downto 0);
			clka : in std_logic;
			clkb : in std_logic;
			dina : in std_logic_vector(7 downto 0);
			doutb : out std_logic_vector(7 downto 0);
			wea : in std_logic
		);
end component;

component receive_state
port	(
			clk16x : in std_logic;
			reset : in std_logic;
			read : in std_logic;
			data : in std_logic_vector(7 downto 0);
			addr_w : out std_logic_vector(4 downto 0)
		);
end component;

signal read : std_logic := '0';
signal data_rx : std_logic_vector(7 downto 0) := (others=>'0');
signal addr_w : std_logic_vector(4 downto 0) := (others=>'0');

signal counter : std_logic_vector(7 downto 0) := (others=>'0');
signal clk16x : std_logic := '0';
signal dsp_are : std_logic := '0';

begin

dsp_are <= not dsp_are_n;

inst_receiver : receiver
port map	(
				clk16x => clk16x,
				reset => reset,
				rx => rx,
				read => read,
				data_out => data_rx
			);

inst_dpram_rx : dpram_rx
port map (
				addra => addr_w,
				addrb => addr_r,
				clka => clk16x,
				clkb => dsp_are,
				dina => data_rx,
				doutb => data_out,
				wea => read
			);
			
inst_receive_state : receive_state
port map	(
				clk16x => clk16x,
				reset => reset,
				read => read,
				data => data_rx,
				addr_w => addr_w
			);
			
process(clk)
begin
if rising_edge(clk) then
	if counter="10100010" then		 -- 50MHz CLK devided by 163 ( 306.75k = 19172 * 16)
		counter <= (others=>'0');
	else
		counter <= counter + 1;
	end if;
end if;
end process;

clk16x <= counter(7);

end Behavioral;