eecadd_4.vhd

此程序采用VHDL语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity eecadd_4 is
port( a: in std_logic_vector(3 downto 0);
    b: in std_logic_vector(3 downto 0);
    cin:in std_logic;
    bcdout: out std_logic_vector(3 downto 0);
    cout:out std_logic );
end eecadd_4;
architecture arch of eecadd_4 is
  signal co:std_logic_vector(3 downto 0);
  signal y,e:std_logic_vector(3 downto 0);
  signal s:std_logic;
  begin
     y(0)<=a(0)xor b(0)xor cin;
     co(0)<=(a(0)and b(0))or(b(0)and cin)or(a(0)and cin);
       gen:for I in 1 to 3 generate
          y(I)<=a(I)xor b(I)xor co(I-1);
          co(I)<=(co(I-1)and a(I)) or (co(I-1)and b(I))or (a(I)and b(I));
     end generate;
 process(a,b,y,co(3))
	begin
     if(y>"1001")then
      e<=y+"0110";
      s<='1';
     elsif (co(3)='1')then
      e<=y+"0110";
      s<='0';
     else
      e<=y;
      s<='0';
     end if;
    cout<=s or co(3);          
    bcdout<=e;
end process;
end arch;