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找到约 10,000 项符合
Logic Analyzer 的代码
shiftrne.vhd
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port (
r : i
divider.vhd
--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
c
shiftlne.vhd
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(
r : in s
fftoutbuf.vhd
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--
use IEEE.math_real.all;
use IEEE.math_complex.all;
library work;
use work.fftDef.all;
--
use work.fftDataType.all;
topclock.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(
clk,reset,set:in std_logic; ---系统时钟、复位、时间设置信号
topclock.vhd.bak
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,reset,set:in std_logic;
S1,m1,h1:in std_logic_vector(1 down
新建 文本文档.txt
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_MFSK is
port(clk :in std_logic; --系统时钟
start :in std
smj_etester.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY smj_etester IS
PORT (BCLK:IN STD_LOGIC;
TCLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CL:I
wave2.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ab is
port ( CLK,CLR: IN STD_LOGIC;
DD : in std_logic_vector(1 downto 0);
LD :
multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS -- 8位乘法器顶层设计
PORT ( P1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);