wave2.vhd

VHDL小程序（本人的一些小成绩哦

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ab is
  port (  CLK,CLR: IN STD_LOGIC;
          DD     : in std_logic_vector(1 downto 0);
          LD     : IN STD_LOGIC_VECTOR(17 DOWNTO 0); 
       OUT1,OUT2 : out INTEGER RANGE 0 TO 255;
         OUT3    : out std_logic_vector(7 downto 0)
       );
end ab;

architecture Behav of ab is
  component FANG
    PORT(CLK:IN STD_LOGIC; 
         CLR:IN INTEGER RANGE 0 TO 1;
         Q:OUT INTEGER RANGE 0 TO 255);
  END COMPONENT;
  COMPONENT FENPIN    
      Port (clr,clk:in std_logic;
                 LD: IN STD_LOGIC_VECTOR( 17 DOWNTO 0 );
               clk1:out std_logic);
  END COMPONENT;
  COMPONENT SANJIAO
    PORT(CLK:IN STD_LOGIC;
         CLR:IN INTEGER RANGE 0 TO 1;
          Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT;
  COMPONENT SIN
    PORT(CLK:IN STD_LOGIC;
         CLR:IN INTEGER RANGE 0 TO 1;
         d:OUT INTEGER RANGE 0 TO 255);
  END COMPONENT;
  COMPONENT YIMA
    PORT (IN1  : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
         OUT11,OUT22,OUT33 : OUT INTEGER RANGE 0 TO 1   );
  END COMPONENT;
  SIGNAL      CLKOUT  : STD_LOGIC;
  SIGNAL    S1,S2,S3  : INTEGER RANGE 0 TO 1;
  SIGNAL        QQ1   :  std_logic_vector(7 downto 0);
BEGIN

  U0 : YIMA    PORT MAP (DD,S1,S2,S3);
  U1 : FENPIN  PORT MAP (clr,clk,LD,CLKOUT);
  U2 : FANG    PORT MAP (CLKOUT,S1,OUT1);
  U3 : SANJIAO PORT MAP (CLKOUT,S2,OUT3);
  U4 : SIN     PORT MAP (CLKOUT,S3,OUT2);
END Behav ;

library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity FENPIN is
      Port (clr,clk:in std_logic;
            LD: IN STD_LOGIC_VECTOR( 17 DOWNTO 0 );
            clk1:out std_logic);
  end FENPIN;
   architecture Behavioral of FENPIN is
   signal cnt:STD_LOGIC_VECTOR(17 DOWNTO 0);
    signal sclk1:std_logic;
   begin
  clk1<=sclk1;
     process(clr,clk)
   begin 
      if clr='1' then
        cnt<="000000000000000000";   
      sclk1<='0';
    elsif(clk'event and clk='1') then
       if cnt=LD then
       sclk1<=not sclk1;
       cnt<="000000000000000000";
       else
       cnt<=cnt+1;
         end if;
     end if;
    end process  ;
  end Behavioral;
CONFIGURATION con1 OF FENPIN IS
FOR Behavioral
END  FOR;
END CON1;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FANG IS
PORT(CLK:IN STD_LOGIC;
    CLR :IN INTEGER  RANGE 0 TO 1;
       Q:OUT INTEGER RANGE 0 TO 255);
END FANG;

ARCHITECTURE SQUARE_ARC OF FANG IS
SIGNAL A:BIT;
BEGIN
PROCESS(CLK,CLR)
VARIABLE CNT:INTEGER;
BEGIN
IF (CLR=0)THEN 
  A<='0';
  ELSIF CLK'EVENT AND CLK='1'THEN
     IF CNT<31 THEN
        CNT:=CNT+1;
     ELSE
        CNT:=0;
        A<=NOT A;
     END IF;
  END IF;
END PROCESS;
PROCESS(CLK,A)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
   IF A='1' THEN
Q<=255;
   ELSE
      Q<=0;
   END IF;
END IF;
END PROCESS;
END SQUARE_ARC;
CONFIGURATION con2 OF FANG IS
FOR SQUARE_ARC
END FOR;
END CON2;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SANJIAO IS
PORT(CLK:IN STD_LOGIC;
      CLR : IN INTEGER RANGE 0 TO 1;
     Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SANJIAO;
ARCHITECTURE SAN_ARC OF SANJIAO IS
BEGIN
PROCESS(CLK,CLR)
VARIABLE TMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE A:STD_LOGIC;
BEGIN
  IF (CLR=0) THEN
     TMP:="00000000";
     ELSIF CLK'EVENT AND CLK='1' THEN
        IF A='0' THEN
        IF TMP="11111000" THEN
           TMP:="11111111";
           A:='1';
        ELSE
           TMP:=TMP+8;
           END IF;
     ELSE
        IF TMP="00000111"THEN
           TMP:="00000000";
           A:='0';
        ELSE
           TMP:=TMP-8;
        END IF;
     END IF;
  END IF;
Q<=TMP;  
END PROCESS;
END SAN_ARC;
CONFIGURATION con3 OF SANJIAO IS
FOR SAN_ARC
END FOR;
END CON3;




LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY YIMA IS
PORT (IN1  : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
      OUT11,OUT22,OUT33 : OUT INTEGER range 0 to 1 );
END YIMA;
ARCHITECTURE ARC OF YIMA IS
BEGIN
PROCESS(IN1)
VARIABLE  OUT1 :integer;
VARIABLE  OUT2 :integer;
VARIABLE  OUT3 :integer;

BEGIN
  IF (IN1="00") THEN 
              OUT1:=1;   OUT2:=0;   OUT3:=0;  out11<=out1; out22<=out1;  out33<=out3;
      ELSE IF (IN1="01")  THEN
               OUT1:=0;OUT2:=1;OUT3:=0; out11<=out1; out22<=out2;  out33<=out3;

      ELSE IF (IN1="10") THEN 
               OUT1:=0;OUT2:=0;OUT3:=1; out11<=out1;  out22<=out1; out33<=out3;       
     END IF;
      END IF;
END IF;
END PROCESS;
END ARC;

CONFIGURATION con5 OF YIMA IS
FOR ARC
END FOR;
END con5;