topclock.vhd

VHDL写的数字钟

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

Entity topclock is
	Port(
        clk,reset,set:in std_logic;   ---系统时钟、复位、时间设置信号
		setm,seth,setd:in std_logic;   --设置分、小时、秒的信号
		Alarm:out std_logic;
		Sec,min,hour:buffer std_logic_vector(7 downto 0);
		Day:out std_logic_vector(2 downto 0)
	);
End;

Architecture one of topclock is

Component second1                                       -- ――秒元件的例化
	 Port(clk,reset:in std_logic;
      Sec:buffer std_logic_vector(7 downto 0);      -- ――秒输出端
      Ensec:out std_logic		 --――秒计时器的进位，用来驱动分计时器
	 ); 
End Component;

Component minute1                                        --――分元件的例化
	Port(
	  clkm,reset:in std_logic;
	  setm:in std_logic;
	  set: in  std_logic;
      min: buffer std_logic_vector(7 downto 0);      -- ―分输出端
      enmin:out std_logic
	 );   
End Component;

Component hour1                                         -- ――时元件的例化
	Port(
	  clkh,set,reset:in std_logic;
      seth:in std_logic;           
      hour:buffer std_logic_vector(7 downto 0);         --――时输出端
      Enhour:out std_logic);  
End Component;

Component day1                                          -- ――星期元件的例化
	Port(
		clkd,set,reset:in std_logic;
		setd:in std_logic;            --――置数端（星期）
		day:buffer std_logic_vector(2 downto 0)
		);     
End Component;

Component alarm1                                        -- ――报时元件的例化
   Port(
	       reset: in std_logic;
           min: in std_logic_vector(7 downto 0);
           alarm:out std_logic
		);
End Component;

signal enm,enh,enda:std_logic;                -- ――秒分、分时、时星期之间的连接信号
signal ena:std_logic_vector(7 downto 0);             --――分与报时之间的连接信号

begin
	u1:second1 port map(reset=>reset,sec=>sec,clk=>clk, ensec=>enm);
	u2:minute1 port map(reset=>reset,set=>set,setm=>setm,min=>min, clkm=>enm,enmin=>enh);
	u3:hour1 port map(reset=>reset,set=>set,seth=>seth,hour=>hour, clkh=>enh,enhour=>enda);
	u4:day1 port map(reset=>reset,set=>set,setd=>setd,day=>day,clkd=>enda);
	u5:alarm1 port map(reset=>reset,min=>min,alarm=>alarm);
end;