multi8x8.vhd

8位相 加乘法器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS                            -- 8位乘法器顶层设计
    PORT ( P1  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
           P3  : OUT STD_LOGIC_VECTOR(7 DOWNTO 2);

           CLKk,hkey : IN STD_LOGIC;
          START : IN STD_LOGIC;
               A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               mmax : out STD_LOGIC_VECTOR(3 DOWNTO 0);
         ARIEND : OUT STD_LOGIC;
           DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END MULTI8X8;
ARCHITECTURE struc OF MULTI8X8 IS
COMPONENT ARICTL
    PORT (  CLK : IN STD_LOGIC;   START : IN STD_LOGIC;
         CLKOUT : OUT STD_LOGIC;  RSTALL : OUT STD_LOGIC;
        ARIEND : OUT STD_LOGIC  );
END COMPONENT;
COMPONENT ANDARITH
    PORT (  ABIN : IN STD_LOGIC;
              DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  );
END COMPONENT;
COMPONENT ADDER8B
    PORT (CIN : IN STD_LOGIC;
             A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          COUT : OUT STD_LOGIC );
END COMPONENT;
COMPONENT SREG8B
    PORT (  CLK : IN STD_LOGIC;   LOAD : IN STD_LOGIC;
             DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
              QB : OUT STD_LOGIC  );
END COMPONENT;
COMPONENT REG16B
    PORT (   CLK : IN STD_LOGIC;  CLR : IN STD_LOGIC;
        D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
        Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)  );
END COMPONENT;
    SIGNAL GNDINT : STD_LOGIC;
    SIGNAL INTCLK : STD_LOGIC;
    SIGNAL RSTALL : STD_LOGIC;
    SIGNAL NEWSTART : STD_LOGIC;	--FOR BETTER
    SIGNAL QB,clk : STD_LOGIC;
    SIGNAL ANDSD : STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL count,maxx : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL DTBIN : STD_LOGIC_VECTOR(8 DOWNTO 0);
    SIGNAL DTBOUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
    DOUT <= DTBOUT;
    GNDINT <= '0';
--  ***** FOR BETTER *****
PROCESS(CLK,START)
BEGIN
	IF START='1' THEN
		NEWSTART<='1';
	ELSIF CLK='0'THEN
		NEWSTART<='0';
	END IF;
END PROCESS;
--*** END FOR BETTER ***
process(hkey)
	begin
		if(hkey'event and hkey='1')then
			maxx<=maxx+'1';
		end if;
end process;
mmax<=maxx;
process(clkk)
begin
	if clkk'event and clkk='1'then
		if(count<maxx)then
			count<=count+'1';
		else
			count<="0000";
			clk<=not clk;
		end if;
	end if;
end process;
--- THE OLD U1 : ARICTL  PORT MAP(CLK => CLK,  START => START,  
U1 : ARICTL  PORT MAP(CLK => CLK,  START => NEWSTART,  --FOR THE BETTER
CLKOUT => INTCLK, RSTALL => RSTALL, ARIEND => ARIEND );
    U2 : SREG8B  PORT MAP( CLK => INTCLK, LOAD => RSTALL,
                               DIN => B, QB => QB  );
    U3 : ANDARITH PORT MAP(ABIN => QB, DIN => A,DOUT => ANDSD);
U4 : ADDER8B  PORT MAP(CIN => GNDINT, 
                A => DTBOUT(15 DOWNTO 8),  B => ANDSD,    
                S => DTBIN(7 DOWNTO 0), COUT => DTBIN(8) );
    U5 : REG16B   PORT MAP(CLK => INTCLK, CLR => RSTALL,
                                 D => DTBIN,  Q => DTBOUT  );
    P1<= "11100111" ;
    P3<= "111111";

END struc;