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Logic Analyzer 的代码
dctslow.vhd
-- Top entity is DCT8_slow
-- ENTITY DCT8_slow IS
-- PORT(
-- clk : IN std_logic ;
-- dctselect : IN std_logic ;
-- din : IN std_logic ;
-- mode
configuring.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity configuring is
port( CLK33 : in std_logic;
NSTATUS : in std_logic;
DA : in std_logic_vector(7
kyosho.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
ck20.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
表决器源代码.txt
-- Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
-- download from: www.pld.com.cn & w
dds.vhd
--DDS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
sum99.vhd
--SUM910.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM99 IS
PORT(K: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK: IN STD_LOGIC;
EN: IN STD_L
command.vhd
--#############################################################################
--
-- LOGIC CORE: Command module
-- MODULE NAME: command()
-- COMPANY: Altera
加法器源程序.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
相应加法器的测试向量（test bench).txt
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------