ck20.vhd

计数时钟芯片代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ck20 is
    Port ( DBUS : in std_logic_vector(7 downto 0);
           RST : in std_logic;
		 ALE : in std_logic;
		 WR : in std_logic;
		 CS : in std_logic_vector(1 downto 0);
		 CLK : in std_logic;
		 H1  : out std_logic_vector(1 downto 0);
		 H0  : out std_logic_vector(3 downto 0);
		 SEC : out std_logic;
		 MIN1: out std_logic_vector(2 downto 0);
		 MIN0: out std_logic_vector(3 downto 0)
		 );
end ck20;

architecture main of ck20 is
component clk_origin
    Port ( CLK : in std_logic;
    		 PCLK : out std_logic);
end component;

component kyosho
    Port ( DBUS : in std_logic_vector(7 downto 0);
           RST : in std_logic;
		 ALE : in std_logic;
		 WR : in std_logic;
		 CS : in std_logic_vector(1 downto 0);
		 PCLK: in std_logic;
		 H1  : out std_logic_vector(1 downto 0);
		 H0  : out std_logic_vector(3 downto 0);
		 SEC : out std_logic;
		 MIN1: out std_logic_vector(2 downto 0);
		 MIN0: out std_logic_vector(3 downto 0)
		 );
end component;

signal PCLK : std_logic;

begin
	
	u1: clk_origin PORT MAP (CLK=>CLK,PCLK=>PCLK); 
	u2: kyosho PORT MAP (DBUS=>DBUS,RST=>RST,ALE=>ALE,WR=>WR,CS=>CS,PCLK=>PCLK,H1=>H1,H0=>H0,SEC=>SEC,MIN1=>MIN1,MIN0=>MIN0);
end main;