kyosho.vhd

计数时钟芯片代码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kyosho is
    Port ( DBUS : in std_logic_vector(7 downto 0);
           RST : in std_logic;
           ALE : in std_logic;
           WR : in std_logic;
           CS : in std_logic_vector(1 downto 0);
           PCLK : in std_logic;
           H1 : out std_logic_vector(1 downto 0);
           H0 : out std_logic_vector(3 downto 0);
           SEC : out std_logic;
           MIN1 : out std_logic_vector(2 downto 0);
           MIN0 : out std_logic_vector(3 downto 0));
end kyosho;

architecture main of kyosho is

signal H1i :integer range 0 to 2:=0;
signal H0i :integer range 0 to 9:=0;
signal SECi :std_logic:='0';
signal MIN1i :integer range 0 to 5:=0;
signal MIN0i :integer range 0 to 9:=0;
signal Hreg1 :integer range 0 to 2:=0;
signal Hreg0 :integer range 0 to 9:=0;
signal Mreg1 :integer range 0 to 5:=0;
signal Mreg0 :integer range 0 to 9:=0;
signal Sreg :integer range 0 to 59:=0;
signal c :integer range 0 to 7:=0; 

begin
H1<=conv_std_logic_vector(H1i,4);
H0<=conv_std_logic_vector(H0i,4);
SEC<=SECi;
MIN1<=conv_std_logic_vector(MIN1i,4);
MIN0<=conv_std_logic_vector(MIN0i,4);

process(PCLK)
begin
if(PCLK' event and PCLK='1') then
	case c is
	when 0=> 	c<=1;
			if(Sreg=59) then 
	         		Mreg0<=Mreg0+1;
				Sreg<=0;
			else Sreg<=Sreg+1;
			end if;
     when 1=> 	c<=2;
			if(Mreg0=9) then
				Mreg1<=Mreg1+1;
				Mreg0<=0;
			else Mreg0<=Mreg0+1;
			end if;
     when 2=> 	c<=3;
			if(Mreg1=6) then
				Hreg0<=Hreg0+1;
				Mreg1<=0;
			else Mreg1<=Mreg1+1;
			end if;
	when 3=>	c<=4;
			SECi<='0';
	when 4=> 	c<=5;
			if(Hreg0=9) then
				Hreg0<=0;
				Hreg1<=Hreg1+1;
			else Hreg0<=Hreg0+1;
			end if;
     when 5=> 	c<=6;
			if(Hreg0=4 and Hreg1=2) then
				Hreg0<=0;
				Hreg1<=0;
			end if;
	when 6=> 	c<=7;
			if(RST='1') then
				Hreg1<=0;
				Hreg0<=0;
				Mreg1<=0;
				Mreg0<=0;
				Sreg<=0;
			end if;
			if(CS="00"and ALE='1' and WR='0') then
				Hreg1<= conv_integer(DBUS(7 downto 4));
				Hreg0<= conv_integer(DBUS(3 downto 0));
	
		     elsif(CS="01"and ALE='1' and WR='0') then
				Mreg1<= conv_integer(DBUS(7 downto 4));
				Mreg0<= conv_integer(DBUS(3 downto 0));
			end if;
	when 7=> 	H1i<=Hreg1;
			H0i<=Hreg0;
			MIN1i<=Mreg1;
			MIN0i<=Mreg0;
			c<=0;
			SECi<='1';
	end case;
end if;
end process;
end main;