表决器源代码.txt

最高优先级编码器 8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述

-- Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways. 
-- download from: www.pld.com.cn & www.fpga.com.cn

ENTITY maj IS
   PORT(a,b,c : IN BIT; m : OUT BIT);
END maj;
--Dataflow style architecture
ARCHITECTURE concurrent OF maj IS
BEGIN
   --selected signal assignment statement (concurrent)
    WITH a&b&c SELECT
        m <= '1' WHEN "110"|"101"|"011"|"111",'0' WHEN OTHERS;
END concurrent;

--Structural style architecture
ARCHITECTURE structure OF maj IS

   --declare components used in architecture
   COMPONENT and2 PORT(in1, in2 : IN BIT; out1 : OUT BIT); 
   END COMPONENT;
   COMPONENT or3 PORT(in1, in2, in3 : IN BIT; out1 : OUT BIT); 
   END COMPONENT;
   --declare local signals
   SIGNAL w1, w2, w3 : BIT;

BEGIN
   --component instantiation statements. 
   --ports of component are mapped to signals 
   --within architecture by position.
   gate1 : and2 PORT MAP (a, b, w1);
   gate2 : and2 PORT MAP (b, c, w2);      
   gate3 : and2 PORT MAP (a, c, w3);      
   gate4 : or3 PORT MAP (w1, w2, w3, m);      
END structure;

--Behavioural style architecture using a look-up table
ARCHITECTURE using_table OF maj IS
BEGIN
   PROCESS(a,b,c)
      CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111";
      VARIABLE index : NATURAL;
   BEGIN
      index := 0; --index must be cleared each time process executes
      IF a = '1' THEN index := index + 1; END IF;
      IF b = '1' THEN index := index + 2; END IF;
      IF c = '1' THEN index := index + 4; END IF;
      m <= lookuptable(index);
   END PROCESS;
END using_table;
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-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity adder is
    port (a    : in std_logic;
          b    : in std_logic;
          cin  : in std_logic;
          sum  : out std_logic;
          cout : out std_logic);
end adder;


-- description of adder using concurrent signal assignments
architecture rtl of adder is
begin
    sum <= (a xor b) xor cin;
    cout <= (a and b) or (cin and a) or (cin and b);
end rtl;


-- description of adder using component instantiation statements
--Miscellaneous Logic Gates 
use work.gates.all;
architecture structural of adder is
    signal xor1_out,
           and1_out,
           and2_out,
           or1_out : std_logic;
begin
    xor1: xorg port map(
                in1  => a,
                in2  => b,
                out1 => xor1_out);
    xor2: xorg port map(
                in1 => xor1_out,
                in2 => cin,
                out1 => sum);
    and1: andg port map(
                in1 => a,
                in2 => b,
                out1   => and1_out);
    or1: org port map(
                in1 => a,
                in2 => b,
                out1   => or1_out);

    and2: andg port map(
                in1 => cin,
                in2 => or1_out,
                out1   => and2_out);
    or2: org port map(
                in1 => and1_out,
                in2 => and2_out,
                out1   => cout);
end structural;


------------------------------------------------------------------------
-- N-bit adder
-- The width of the adder is determined by generic N
------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity adderN is
    generic(N : integer := 16);
    port (a    : in std_logic_vector(N downto 1);
          b    : in std_logic_vector(N downto 1);
          cin  : in std_logic;
          sum  : out std_logic_vector(N downto 1);
          cout : out std_logic);
end adderN;

-- structural implementation of the N-bit adder
architecture structural of adderN is
    component adder
        port (a    : in std_logic;
              b    : in std_logic;
              cin  : in std_logic;
              sum  : out std_logic;
              cout : out std_logic);
    end component;

    signal carry : std_logic_vector(0 to N);
begin
    carry(0) <= cin;
    cout <= carry(N);

    -- instantiate a single-bit adder N times
    gen: for I in 1 to N generate
        add: adder port map(
                a => a(I),
                b => b(I),
                cin => carry(I - 1),
                sum => sum(I),
                cout => carry(I));
   end generate;
end structural;


-- behavioral implementation of the N-bit adder
architecture behavioral of adderN is
begin
    p1: process(a, b, cin)
        variable vsum : std_logic_vector(N downto 1);
        variable carry : std_logic;
    begin
        carry := cin;
        for i in 1 to N loop
            vsum(i) := (a(i) xor b(i)) xor carry;
            carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
        end loop;
        sum <= vsum;
        cout <= carry;
    end process p1;
end behavioral;
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