configuring.vhd

intel flash控制器VHDL 源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity configuring is
	port( CLK33	: in std_logic;
	      NSTATUS	: in std_logic;
	      DA	: in std_logic_vector(7 downto 0);
	      RSTB   	: in std_logic;
	      CONF_DONE	: in std_logic;
	      CONF_ST	: in std_logic;
	      MODE_U	: in std_logic;
	      DATA0	: out std_logic;
	      DCLK	: out std_logic;
	      NCONFIG	: out std_logic;
	      CONF_ADD	: out std_logic_vector(21 downto 0);
	      C_OEN	: out std_logic;
	      CONF_END	: out std_logic;
	      C_ERR	: out std_logic;
	      CONF_ERR	: out std_logic 
	     );
end;

architecture rtl of configuring is

---------------------------------------------------------------------------------------------------
constant START 		:std_logic_vector(3 downto 0) := "1000";
constant WAIT_NCFG_8us	:std_logic_vector(3 downto 0) := "1100";
constant STATUS		:std_logic_vector(3 downto 0) := "1001";
constant WAIT_40us	:std_logic_vector(3 downto 0) := "1101";
constant CONFIG		:std_logic_vector(3 downto 0) := "0011";
constant WAIT_NCFG	:std_logic_vector(3 downto 0) := "0101";
constant ADD_1H		:std_logic_vector(21 downto 0) := "0000000000000000000001" ;
---------------------------------------------------------------------------------------------------

signal PP	     :std_logic_vector(3 downto 0);
signal CNT3B	     :std_logic_vector(2 downto 0);
signal DATA0_INT     :std_logic;
signal DCLK_INT	     :std_logic;
signal INC	     :std_logic_vector(21 downto 0);
signal WAITD	     :std_logic_vector(10 downto 0);
signal RD	     :std_logic_vector(7 downto 0);
signal CNT2B	     :std_logic_vector(1 downto 0);
signal C_ERR0	     :std_logic ;
signal TEMP_CONF_ERR :std_logic ;

signal CONFIG_EN     :std_logic ;
signal CRY_3         :std_logic ;
signal CRY_7         :std_logic ;
signal CO            :std_logic ;
signal CONF_ERREN    :std_logic ;

begin

	CONFIG_EN <= ((CONF_ST) and not(TEMP_CONF_ERR)) ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			PP    <= START;
			CNT3B <= (others => '0');
			CNT2B <= (others => '0');
			INC   <= ADD_1H ;
			WAITD <= (others => '0');
		else
		if (CLK33'event and CLK33='1') then
			if (CONFIG_EN='1') then
				case PP is 
				when START =>
						CNT2B <= (others => '0');
						CNT3B <= (others => '0');
						INC   <= ADD_1H ;
						WAITD <= (others => '0');
						PP    <= WAIT_NCFG_8us;

				when WAIT_NCFG_8us =>
						CNT2B <= (others => '0');
						CNT3B <= (others => '0');
						INC   <= ADD_1H ;
						WAITD <= WAITD + 1;
					if WAITD = "00011111010" then
						PP    <= STATUS;
					end if;

				when STATUS =>
						CNT2B <= (others => '0');
						CNT3B <= (others => '0');
						INC   <= ADD_1H ;
						WAITD <= (others => '0');
						PP    <= WAIT_40us;

				when WAIT_40us =>
						CNT2B <= (others => '0');
						CNT3B <= (others => '0');
						INC   <= ADD_1H ;
						WAITD <= WAITD + 1;
					if WAITD = "10011100010" then
						PP    <= WAIT_NCFG;
					end if;

				when WAIT_NCFG =>
						CNT3B <= (others => '0');
						INC   <= ADD_1H ;
						WAITD <= (others => '0');
						CNT2B <= CNT2B + 1;
					if CNT2B = "11"  then
						PP    <= CONFIG;
					end if;

				when CONFIG =>
						CNT2B   <= (others => '0');
					if CONF_DONE='1' then
						WAITD <= WAITD + 1;
					else
						CNT3B <= CNT3B + 1;
					end if;

					if CNT3B= "011" then
						INC   <= INC + 1;
					end if;
					if (NSTATUS ='0')then
						PP    <= START ;
					elsif WAITD = "00011111010" then
						PP    <= START ;
					end if;

				when others =>
						PP    <= START;
						CNT2B   <= (others => '0') ;
						WAITD <= (others => '0') ;
						INC   <= ADD_1H ;
						CNT3B <= (others => '0') ;
				end case;
			end if;
		end if;
	end if;
	end process;

	DCLK_INT <= (not(CLK33))  when PP=CONFIG else '0';

	CRY_7 <= '1' when CNT3B="111" else '0' ;
	CRY_3 <= '1' when CNT2B="11" else '0' ;
	CO <= CRY_3 or CRY_7 ;

	process (CLK33, RSTB) begin
		if (RSTB='0')then
			RD(7) <= '0';
			RD(6) <= '0';
			RD(5) <= '0';
			RD(4) <= '0';
			RD(3) <= '0';
			RD(2) <= '0';
			RD(1) <= '0';
			RD(0) <= '0';
		elsif (CLK33'event and CLK33='1')then
			if (CO='1') then
				RD(7) <= DA(7) ;
				RD(6) <= DA(6) ;
				RD(5) <= DA(5) ;
				RD(4) <= DA(4) ;
				RD(3) <= DA(3) ;
				RD(2) <= DA(2) ;
				RD(1) <= DA(1) ;
				RD(0) <= DA(0) ;
			else
				RD(7) <= '0' ;
				RD(6) <= RD(7) ;
				RD(5) <= RD(6) ;
				RD(4) <= RD(5) ;
				RD(3) <= RD(4) ;
				RD(2) <= RD(3) ;
				RD(1) <= RD(2) ;
				RD(0) <= RD(1) ;
			end if ;
		end if ;
	end process ;

	DATA0_INT <= RD(0) ;

	NCONFIG <= '0' when PP=WAIT_NCFG_8us else '1' ;
	DCLK  <= '0' when PP(1)='0' else DCLK_INT ;
	DATA0 <= '0' when PP(1)='0' else DATA0_INT ;
	CONF_ADD <= INC;
	C_OEN <= CONF_DONE or PP(3) ;
	CONF_END <= '1' when ((PP = CONFIG) and (WAITD = "00011111010")) else '0';

	CONF_ERREN <= '1' when ((PP(1)='1') and (NSTATUS='0')) else '0' ;

	process (CLK33, RSTB) begin
		if (RSTB='0')then
			TEMP_CONF_ERR <= '0' ;
		elsif (CLK33' event and CLK33='1')then
			if (MODE_U='1')then
				TEMP_CONF_ERR <= '0' ;
			elsif (CONF_ERREN='1') then
				TEMP_CONF_ERR <= '1' ;
			end if ;
		end if ;
	end process ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			C_ERR0 <= '0' ;
		elsif (CLK33' event and CLK33='1') then
			C_ERR0 <= TEMP_CONF_ERR ;
		end if ;
	end process ;

	C_ERR <= (TEMP_CONF_ERR) and not(C_ERR0) ;

	CONF_ERR <= TEMP_CONF_ERR ;
end;