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Logic Analyzer 的代码
reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
pc.vhd
-- pc.vhd
-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is assert
uartrec.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity UartRec is
Port(
RESET :in std_logic;
RCLK :in std_logic;
ptxd.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PTXD is
Port(
TCLK,Reset :in std_logic;
SendEn,Clock:in std_logic;
INT :in std_logic;
pcm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity PCM is
Port(
Reset :in std_logic;
PCLK :in std_logic;
S_Data :in std_
pcm.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity PCM is
Port(
Reset :in std_logic;
PCLK :in std_logic;
S_Data :in std_
uartsend.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity UartSend is
port(
Reset : in std_logic ;
SendClk : in std_logic ;
Data
uartsend.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity UartSend is
port(
Reset : in std_logic ;
SendClk : in std_logic ;
Data
main.vhd
--************************************************************
--
-- Project Name: Timer
-- File Name : main.vhd(top level)
-- Function : This is a basic timer,
-- use 2 key to adjust
keydetc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keydetc is
Port ( clk_5ms :in std_logic;
-- clk_1us :in std_logic;