uartsend.vhd

PCM数据采集

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity UartSend is

port( 
	Reset	: in std_logic ;
	SendClk	: in std_logic ;
	Data	: in std_logic_vector(8 downto 0);
	Latch	: in std_logic ;
	UartOut	: out std_logic ;
	Busy	: out std_logic  
	);

end;

architecture ART_UartSend of UartSend is
	signal SendComp	:std_logic;
	signal Start	:std_logic;
	begin
	
	process(Reset, SendComp, Latch)
	begin
		if Reset = '0' or SendComp = '0' then
			Start <= '0' ;
		elsif Latch'event and Latch = '1' then
			Start <= '1' ;
		end if;
	end process;
	
	process(SendClk, Reset)
	        variable Tstate		:std_logic_vector(3 downto 0);
	        variable SendBuffer	:std_logic_vector(8 downto 0);
	        variable lastLatch	:std_logic;
	    begin   -----------------------------------------TXD process
	    if Reset = '0' then
	        UartOut <= '1';
	        SendComp <= '1';
--	        lastLatch :='1';
	        Tstate := (others => '0');
	        SendBuffer :=(others => '0');
	    elsif SendClk'event and SendClk='1' then
	    	if Start = '1' then
	    		SendBuffer := Data;
	    		SendComp <= '0';
	    		UartOut <= '0';
	    		Tstate := "0111";
	    	elsif Tstate /= "0000" then
	        	UartOut <= SendBuffer(0);
	        	SendBuffer := '1' & SendBuffer(8 downto 1);
	          	Tstate := Tstate + 1;
	        else 
	        	UartOut <= '1';
	        	SendComp <= '1';
	        end if;
--	        lastLatch := Latch;
	    end if;
	end process;
	
	Busy <= SendComp;

end ART_UartSend;