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Logic Analyzer 的代码
write.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity write is port(
clk,rst,
);
end write;
architecture a of write is
begin
end a;
entity read is port(
clk,rst,lint2,wrfull: in
int.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity int is port(
lint : in std_logic;
clk,rst : in std_logic;
lint1,lint2 : b
ir_pen_main.vhd
--============================================================================
-- Project : IR Pen Control
-- Programmer : Byungchan Son
-- Function :
-- Language : VHDL
--==================
omet.vhd
--omet.vhd
--v0.1
--measure dff
library ieee;
use ieee.std_logic_1164.all;
entity omet is
port(
clk: in std_logic;
reset: in std_logic;
imet_0: in std_logic_vector(5 downto 0);
last.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity last is
port (xuanzhe:in std_logic;
m1 :in std_logic_vector (17 downto 0);
m2 :in std_logic_ve
jiafa.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity adder18 is
generic(N : integer := 16);
port (a : in std_logic_vector(18 downto 1);
b : in std_logic_vector(18 downto 1);
tf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TF IS
PORT (EN,CLK,CLR:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END;
ARCHITECTURE BHV OF TF I
bzh.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BZH IS
PORT (EN,CLK,CLR:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END;
ARCHITECTURE BHV OF BZH
mc8051_ram.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
scan4digit.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:14 11/17/2008
-- Design Name:
-- Module Name: scan4digit