jiafa.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 48 行

library IEEE;
use IEEE.std_logic_1164.all;
entity adder18 is
    generic(N : integer := 16);
    port (a    : in std_logic_vector(18 downto 1);
          b    : in std_logic_vector(18 downto 1);
          cin  : in std_logic;
          sum  : out std_logic_vector(18 downto 1);
          cout : out std_logic);
end adder18;
architecture structural of adder18 is
    component adder
        port (a    : in std_logic;
              b    : in std_logic;
              cin  : in std_logic;
              sum  : out std_logic;
              cout : out std_logic);
    end component;
 signal carry : std_logic_vector(0 to 18);
begin
    carry(0) <= cin;
    cout <= carry(18);
gen: for I in 1 to 18 generate
        add: adder port map(
                a => a(I),
                b => b(I),
                cin => carry(I - 1),
                sum => sum(I),
                cout => carry(I));
   end generate;
end structural;
architecture behavioral of adder18 is
begin
    p1: process(a, b, cin)
        variable vsum : std_logic_vector(18 downto 1);
        variable carry : std_logic;
    begin
        carry := cin;
        for i in 1 to  18 loop
            vsum(i) := (a(i) xor b(i)) xor carry;
            carry := (a(i) and b(i)) or (carry and (a(i) or b(i)));
        end loop;
        sum <= vsum;
        cout <= carry;
    end process p1;
end behavioral;