last.vhd

来自「用FPGA做的DDS函数信号发生器」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity last is 
    port (xuanzhe:in std_logic;
      m1 :in std_logic_vector (17 downto 0);
      m2 :in std_logic_vector (41 downto 0);
      x : out std_logic_vector(19 downto 0);
      m3 :in std_logic);
    end last;
ARCHITECTURE ART OF last IS
begin
   process(xuanzhe,m3)
     begin
  if xuanzhe='0' then 
        x<="00"&m1;
 elsif xuanzhe='1' then
     if ( m3='1' ) then 
        x<=m2(19 downto 0)+1;
     else
         x<=m2(19 downto 0);
      end if  ;
  end if ;
  end process;
end art;