ir_pen_main.vhd

infra pen controller, cmos sensor control and sdram control

--============================================================================
-- Project 		: IR Pen Control
-- Programmer	: Byungchan Son
-- Function		: 
-- Language		: VHDL
--============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--============================================================================
-- 涝免仿 器飘 沥狼
--============================================================================
entity ir_pen_main is
	port(
		-- system signal
		reset_n : in std_logic;
		clock_in : in std_logic;
		clock_wd0 : in std_logic;
		clock_wd1 : in std_logic;
		clock_wd2 : in std_logic;
		clock_wd3 : in std_logic;
		-- video input ( YUV 4:2:2 )
		cmos_y : in std_logic_vector(7 downto 0);
		cmos_vs : in std_logic;
		cmos_hs : in std_logic;
		cmos_mclk : out std_logic;
		cmos_mclk1 : in std_logic;
		cmos_mclk2 : out std_logic;
		cmos_reset : out std_logic;
		cmos_fsin : out std_logic;
		-- sdram
		sda : out std_logic_vector(12 downto 0);
		sdd : inout std_logic_vector(15 downto 0);
		sdba : out std_logic_vector(1 downto 0);
		sdqm : out std_logic_vector(1 downto 0);
		sdcas_n : out std_logic;
		sdras_n : out std_logic;
		sdwe_n : out std_logic;
		sdcs_n : out std_logic;
		sdcke : out std_logic;
		sdclk : out std_logic;
		-- COM port
--		usb_rst_n : out std_logic;
		usb_data : inout std_logic_vector(7 downto 0);
		usb_rxf : in std_logic;
		usb_txe : in std_logic;
		usb_rd_n : out std_logic;
		usb_wr : out std_logic;
		usb_siwu : out std_logic;
		-- 促捞坷靛 力绢
		led_connect : out std_logic;
		led_power : out std_logic;
		-- i2c signal
		i2c_scl : out std_logic;
		i2c_sda : inout std_logic;
		-- FT245
		ft245_clk : out std_logic;
		-- test
		test_out : out std_logic
		);
end ir_pen_main;
--============================================================================
-- 备炼 沥狼
--============================================================================
architecture ir_pen_main_a of ir_pen_main is
--------------------------------------------------------------------
-- 郴何 葛碘
--------------------------------------------------------------------
component osd_pll
	PORT
	(
		inclk0	: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		c1		: OUT STD_LOGIC
	);
END component;
component cmos_control
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- ir pen main
		cmos_y : in std_logic_vector(7 downto 0);
		cmos_vs : in std_logic;
		cmos_hs : in std_logic;
		cmos_mclk : out std_logic;
		cmos_reset : out std_logic;
		-- 促捞坷靛 力绢
		led_connect : out std_logic;
		led_power : out std_logic;
		-- uart
		com_rx_data : in std_logic_vector(31 downto 0);
		com_rx_req : in std_logic;
		com_rx_ack : out std_logic;
		com_tx_data : out std_logic_vector(31 downto 0);
		com_tx_req : out std_logic;
		com_tx_ack : in std_logic;
		image_tx_req : out std_logic_vector(1 downto 0);
		image_tx_ack : in std_logic;
		image_tx_no : out std_logic_vector(3 downto 0);
		sync_image_tx_req : out std_logic;
		pos_image_tx_req : out std_logic;
		pos_image_tx_ack : in std_logic;
		-- data control
		write_addr : out std_logic_vector(11 downto 0);
		write_data : out std_logic_vector(7 downto 0);
		read_data : in std_logic_vector(7 downto 0);
		write_data_req : out std_logic;
		write_data_ack : in std_logic;
		read_data_req : out std_logic;
		read_data_ack : in std_logic;
		-- sdram control
		buff_data : out std_logic_vector(127 downto 0);
		buff_wrreq : out std_logic;
		buff_rdreq : out std_logic;
		buff_rdack : in std_logic;
		buff_acer : out std_logic;
		buff_reset : out std_logic;
		pos_image_address : out std_logic_vector(23 downto 0);
		pos_image_read_req : out std_logic;
		pos_image_read_ack : in std_logic;
		-- test
		wdt0_signal : in std_logic;
		test_out : out std_logic
		);
end component;

component sdram_control
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- capture main : sdram signal
		sda : out std_logic_vector(12 downto 0);
		sdd_in : in std_logic_vector(15 downto 0);
		sdd_out : out std_logic_vector(15 downto 0);
		sdd_hz : out std_logic;
		sdba : out std_logic_vector(1 downto 0);
		sdqm : out std_logic_vector(1 downto 0);
		sdcas : out std_logic;
		sdras : out std_logic;
		sdwe : out std_logic;
		sdcs : out std_logic;
--		sdcke : out std_logic;
		sdclk : out std_logic;
		-- cmos control
		buff_data : in std_logic_vector(127 downto 0);
		buff_wrreq : in std_logic;
		buff_rdreq : in std_logic;
		buff_rdack : out std_logic;
		buff_acer : in std_logic;
		buff_reset : in std_logic;
		pos_image_address : in std_logic_vector(23 downto 0);
		pos_image_read_req : in std_logic;
		pos_image_read_ack : out std_logic;
		-- uart
		image_data : out std_logic_vector(127 downto 0)
		-- test signal
		);
end component;

component asynchronous_receiver_transmitter
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- ir pen main
		usb_data_out : out std_logic_vector(7 downto 0);
		usb_data_in : in std_logic_vector(7 downto 0);
		usb_data_hz : out std_logic;
		usb_rxf : in std_logic;
		usb_txe : in std_logic;
		usb_rd_n : out std_logic;
		usb_wr : out std_logic;
		-- cmos control
		com_rx_data : out std_logic_vector(31 downto 0);
		com_rx_req : out std_logic;
		com_rx_ack : in std_logic;
		com_tx_data : in std_logic_vector(31 downto 0);
		com_tx_req : in std_logic;
		com_tx_ack : out std_logic;
		image_tx_req : in std_logic_vector(1 downto 0);
		image_tx_ack : out std_logic;
		image_tx_no : in std_logic_vector(3 downto 0);
		sync_image_tx_req : in std_logic;
		pos_image_tx_req : in std_logic;
		pos_image_tx_ack : out std_logic;
		-- sdram control
		image_data : in std_logic_vector(127 downto 0)
		);
end component;
component i2c_control
	port(
		-- 矫胶袍 脚龋
		reset : in std_logic;
		clock : in std_logic;
		-- data control
		write_addr : in std_logic_vector(11 downto 0);
		write_data : in std_logic_vector(7 downto 0);
		read_data : out std_logic_vector(7 downto 0);
		write_data_req : in std_logic;
		write_data_ack : out std_logic;
		read_data_req : in std_logic;
		read_data_ack : out std_logic;
		-- I2C
		i2c_scl : out std_logic;
		i2c_sda_in : in std_logic;
		i2c_sda_out : out std_logic;
		i2c_sda_enable : out std_logic
		);
end component;
--------------------------------------------------------------------
-- 郴何 脚龋
--------------------------------------------------------------------
signal reset : std_logic;
signal clock : std_logic;
signal com_rx_data : std_logic_vector(31 downto 0);
signal com_rx_req : std_logic;
signal com_rx_ack : std_logic;
signal com_tx_data : std_logic_vector(31 downto 0);
signal com_tx_req : std_logic;
signal com_tx_ack : std_logic;
signal i2c_sda_in : std_logic;
signal i2c_sda_out : std_logic;
signal i2c_sda_enable : std_logic;
signal write_addr : std_logic_vector(11 downto 0);
signal write_data : std_logic_vector(7 downto 0);
signal read_data : std_logic_vector(7 downto 0);
signal write_data_req : std_logic;
signal write_data_ack : std_logic;
signal read_data_req : std_logic;
signal read_data_ack : std_logic;
signal buff_data : std_logic_vector(127 downto 0);
signal buff_wrreq : std_logic;
signal buff_rdreq : std_logic;
signal buff_rdack : std_logic;
signal buff_acer : std_logic;
signal buff_reset : std_logic;
signal image_tx_req : std_logic_vector(1 downto 0);
signal image_tx_ack : std_logic;
signal image_data : std_logic_vector(127 downto 0);
signal sdd_in : std_logic_vector(15 downto 0);
signal sdd_out : std_logic_vector(15 downto 0);
signal sdcas : std_logic;
signal sdras : std_logic;
signal sdwe : std_logic;
signal sdcs : std_logic;
signal sdd_hz : std_logic;
signal clk_6m : std_logic;
signal clk_12m : std_logic;
signal usb_data_out : std_logic_vector(7 downto 0);
signal usb_data_in : std_logic_vector(7 downto 0);
signal usb_data_hz : std_logic;
signal pos_image_address : std_logic_vector(23 downto 0);
signal pos_image_read_req : std_logic;
signal pos_image_read_ack : std_logic;
signal sync_image_tx_req : std_logic;
signal pos_image_tx_req : std_logic;
signal pos_image_tx_ack : std_logic;
signal wdt0_signal : std_logic;
signal image_tx_no : std_logic_vector(3 downto 0);
--------------------------------------------------------------------
-- 橇肺技辑 矫累
--------------------------------------------------------------------
begin
	m0 : osd_pll
	port map(
		-- system signal
		inclk0 => clock_in,
		c0 => clk_12m,
		c1 => clock
		);
	m1 : cmos_control
	port map(
		-- system signal
		reset => reset,
		clock => clock,
		-- ir pen main
		cmos_y => cmos_y,
		cmos_vs => cmos_vs,
		cmos_hs => cmos_hs,
		cmos_mclk => cmos_mclk2,
		cmos_reset => cmos_reset,
		-- 促捞坷靛 力绢
		led_connect => led_connect,
		led_power => led_power,
		-- uart
		com_rx_data => com_rx_data,
		com_rx_req => com_rx_req,
		com_rx_ack => com_rx_ack,
		com_tx_data => com_tx_data,
		com_tx_req => com_tx_req,
		com_tx_ack => com_tx_ack,
		image_tx_req => image_tx_req,
		image_tx_ack => image_tx_ack,
		image_tx_no => image_tx_no,
		sync_image_tx_req => sync_image_tx_req,
		pos_image_tx_req => pos_image_tx_req,
		pos_image_tx_ack => pos_image_tx_ack,
		-- data control
		write_addr => write_addr,
		write_data => write_data,
		read_data => read_data,
		write_data_req => write_data_req,
		write_data_ack => write_data_ack,
		read_data_req => read_data_req,
		read_data_ack => read_data_ack,
		-- sdram control
		buff_data => buff_data,
		buff_wrreq => buff_wrreq,
		buff_rdreq => buff_rdreq,
		buff_rdack => buff_rdack,
		buff_acer => buff_acer,
		buff_reset => buff_reset,
		pos_image_address => pos_image_address,
		pos_image_read_req => pos_image_read_req,
		pos_image_read_ack => pos_image_read_ack,
		-- test
		wdt0_signal => wdt0_signal,
		test_out => test_out
		);
	m2 : sdram_control
	port map(
		-- system signal
		reset => reset,
		clock => clock,
		-- capture main : sdram signal
		sda => sda,
		sdd_in => sdd_in,
		sdd_out => sdd_out,
		sdd_hz => sdd_hz,
		sdba => sdba,
		sdqm => sdqm,
		sdcas => sdcas,
		sdras => sdras,
		sdwe => sdwe,
		sdcs => sdcs,
--		sdcke => sdcke,
		sdclk => sdclk,
		-- cmos control
		buff_data => buff_data,
		buff_wrreq => buff_wrreq,
		buff_rdreq => buff_rdreq,
		buff_rdack => buff_rdack,
		buff_acer => buff_acer,
		buff_reset => buff_reset,
		pos_image_address => pos_image_address,
		pos_image_read_req => pos_image_read_req,
		pos_image_read_ack => pos_image_read_ack,
		-- uart
		image_data => image_data
		-- test signal
		);
	m3 : asynchronous_receiver_transmitter
	port map(
		-- system signal
		reset => reset,
		clock => clock,
		-- ir pen main
		usb_data_out => usb_data_out,
		usb_data_in => usb_data_in,
		usb_data_hz => usb_data_hz,
		usb_rxf => usb_rxf,
		usb_txe => usb_txe,
		usb_rd_n => usb_rd_n,
		usb_wr => usb_wr,
		-- cmos control
		com_rx_data => com_rx_data,
		com_rx_req => com_rx_req,
		com_rx_ack => com_rx_ack,
		com_tx_data => com_tx_data,
		com_tx_req => com_tx_req,
		com_tx_ack => com_tx_ack,
		image_tx_req => image_tx_req,
		image_tx_ack => image_tx_ack,
		image_tx_no => image_tx_no,
		sync_image_tx_req => sync_image_tx_req,
		pos_image_tx_req => pos_image_tx_req,
		pos_image_tx_ack => pos_image_tx_ack,
		-- sdram control
		image_data => image_data
		);
	m4 : i2c_control
	port map(
		-- system signal
		reset => reset,
		clock => clock,
		-- data control
		write_addr => write_addr,
		write_data => write_data,
		read_data => read_data,
		write_data_req => write_data_req,
		write_data_ack => write_data_ack,
		read_data_req => read_data_req,
		read_data_ack => read_data_ack,
		-- I2C
		i2c_scl => i2c_scl,
		i2c_sda_in => i2c_sda_in,
		i2c_sda_out => i2c_sda_out,
		i2c_sda_enable => i2c_sda_enable
		);
	-------------------------------------------------------------------------
	-- 橇肺技辑 矫累
	-------------------------------------------------------------------------
	-- SDRAM 滚胶 免仿
	sdram_bus : process(sdd_hz,sdd,sdd_out)
	begin
		if(sdd_hz = '1')then
			sdd <= (others => 'Z');
		else
			sdd <= sdd_out;
		end if;
	end process;
	i2c_signal : process(
		reset,
		i2c_sda_enable,
		i2c_sda_out,
		i2c_sda,
		usb_data_hz,
		usb_data_out
		)
	begin
		if(reset = '1')then
			-- HV7131GP i2c 免仿
			i2c_sda <= 'Z';
			cmos_fsin <= '0';
		else
			-- HV7131GP i2c 免仿
			if(i2c_sda_enable = '1')then
				i2c_sda <= i2c_sda_out;
			else
				i2c_sda <= 'Z';
				i2c_sda_in <= i2c_sda;
			end if;
			-- ft245
			if(usb_data_hz = '1')then
				usb_data <= (others => 'Z');
			else
				usb_data <= usb_data_out;
			end if;
		end if;
	end process;
	clock_ft245 : process(
		reset,
		clk_12m,
		clk_6m
		)
	begin
		if(reset = '1')then
			-- HV7131GP i2c 免仿
			clk_6m <= '0';
		elsif(clk_12m'event and clk_12m = '1')then
			clk_6m <= not clk_6m;
		end if;
	end process;
	clock_wdt0 : process(
		reset,
		clock_wd0,
		wdt0_signal
		)
	begin
		if(reset = '1')then
			wdt0_signal <= '0';
		elsif(clock_wd0'event and clock_wd0 = '1')then
			wdt0_signal <= not wdt0_signal;
		end if;
	end process;
	----------------------------------------------------------------
	-- 肺流 脚龋
	----------------------------------------------------------------
	reset <= not reset_n;
--	usb_rst_n <= reset_n;
	sdcas_n <= not sdcas;
	sdras_n <= not sdras;
	sdwe_n <= not sdwe;
	sdcs_n <= not sdcs;
	sdcke <= '1';
	sdd_in <= sdd;
	ft245_clk <= clk_6m;
	usb_data_in <= usb_data;
	usb_siwu <= '1';
--	cmos_mclk2 <= not cmos_mclk1;
end ir_pen_main_a;
--============================================================================
-- 场
--============================================================================