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Logic Analyzer 的代码
cannon.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cannon is
Port ( clk : in std_logic;
reset : in std_logic;
top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port ( sysclk : in std_logic;
resn : in std_logic;
v5_2.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_2 is
port(sel : in std_logic_vector(2 downto 0);
a : in std_logic;
b : in std_logic;
c : in std_logic;
v5_5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V5_5 is
port(a : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logi
v5_31.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_31 is
port(sel : in std_logic_vector(1 downto 0);
a : in std_logic;
b : in std_logic;
c : in std_lo
dctslow.vhd
-- Top entity is DCT8_slow
-- ENTITY DCT8_slow IS
-- PORT(
-- clk : IN std_logic ;
-- dctselect : IN std_logic ;
-- din : IN std_logic ;
--
dctslow.vhd
-- Top entity is DCT8_slow
-- ENTITY DCT8_slow IS
-- PORT(
-- clk : IN std_logic ;
-- dctselect : IN std_logic ;
-- din : IN std_logic ;
--
hsata.vhd
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Copyright (C) 2004 Free Model Foundry; ht
dsata.vhd
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Copyright (C) 2004 Free Model Foundry; ht
cnt_12.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_12 IS
PORT(CLK :IN STD_LOGIC;
reset :IN STD_LOGIC;
en :IN STD_LOGIC;
co:OUT STD_ULOGIC;