v5_31.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V5_31 is
port(sel     : in std_logic_vector(1 downto 0);
     a       : in  std_logic;
     b       : in  std_logic;
     c       : in  std_logic;
     d       : in  std_logic;
     Dataout : out std_logic);
end V5_31;

architecture a of V5_31 is
	
begin
    
    with sel select
		Dataout  <= b when "01" ,
					c when "10" , 
	                d when "11" ,					
					a when others;   	 
    
end a;